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2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)最新文献

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MS-EMC vs. NEGF: A comparative study accounting for transport quantum corrections MS-EMC与NEGF:考虑输运量子修正的比较研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-05-07 DOI: 10.1109/ULIS.2018.8354758
C. Medina-Bailón, C. Sampedro, J. Padilla, A. Godoy, L. Donetti, F. Gámiz, A. Asenov
{"title":"MS-EMC vs. NEGF: A comparative study accounting for transport quantum corrections","authors":"C. Medina-Bailón, C. Sampedro, J. Padilla, A. Godoy, L. Donetti, F. Gámiz, A. Asenov","doi":"10.1109/ULIS.2018.8354758","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354758","url":null,"abstract":"As electronic devices approach the nanometer scale, quantum transport theories have been recognized as the best option to reproduce their performance. Other possible trend, mainly focused on reducing the computational effort, is the inclusion of quantum effects in semi-classical simulators. This work presents a comparison between a NEGF simulator and a MS-EMC tool including S/D tunneling both applied on a DGSOI transistor.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
New method for self-heating estimation using only DC measurements 仅使用直流测量的自热估计新方法
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-05-03 DOI: 10.1109/ULIS.2018.8354756
C. A. Mori, P. Agopian, J. Martino
{"title":"New method for self-heating estimation using only DC measurements","authors":"C. A. Mori, P. Agopian, J. Martino","doi":"10.1109/ULIS.2018.8354756","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354756","url":null,"abstract":"This paper reports a new method for estimating the thermal resistance of a device using the inverse of the transistor efficiency as a function of the power applied to the transistor's channel. The advantages of this new method are the use of DC measurements only and errors smaller than 4% in the estimation of the channel temperature increase due to the SHE when compared to a pulsed method for the UTBB SOI studied in this work.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133807999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Towards a magnetoresistance characterization methodology for 1D nanostructured transistors 一维纳米结构晶体管的磁阻表征方法研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-05-03 DOI: 10.1109/ULIS.2018.8354750
G. Umana-Membreno, N. Akhavan, J. Antoszewski, L. Faraone, S. Cristoloveanu
{"title":"Towards a magnetoresistance characterization methodology for 1D nanostructured transistors","authors":"G. Umana-Membreno, N. Akhavan, J. Antoszewski, L. Faraone, S. Cristoloveanu","doi":"10.1109/ULIS.2018.8354750","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354750","url":null,"abstract":"A novel approach to magnetoresistance characterization of ID-like nanoscaled transistor structures is presented. The proposed approach, which is based on the physical magnetoresistance effect (PMR), exploits the reality that carriers have non-discrete velocity distributions even when only a single carrier species is present.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132519790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of the 1D Scattering Mechanisms' Impact on the Mobility in Si Nanowire Transistors 一维散射机制对硅纳米线晶体管迁移率影响的研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-05-03 DOI: 10.1109/ULIS.2018.8354723
C. Medina-Bailón, T. Sadi, M. Nedjalkov, J. Lee, S. Berrada, H. Carrillo-Nuñez, V. Georgiev, S. Selberherr, A. Asenov
{"title":"Study of the 1D Scattering Mechanisms' Impact on the Mobility in Si Nanowire Transistors","authors":"C. Medina-Bailón, T. Sadi, M. Nedjalkov, J. Lee, S. Berrada, H. Carrillo-Nuñez, V. Georgiev, S. Selberherr, A. Asenov","doi":"10.1109/ULIS.2018.8354723","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354723","url":null,"abstract":"The extensive research of aggressively scaled nano-electronic devices necessitates the inclusion of quantum confinement effects and their impact on performance. This work implements a set of multisubband phonon and impurity scattering mechanisms within the Kubo-Greenwood formalism in order to study their impact on the mobility in Si nanowire transistors (NWTs). This 1D treatment has been coupled with a 3D Poisson-2D Schrödinger solver, which accurately captures the effects of quantum confinement on charge dynamics. We also emphasize the importance of using the 1D models to evaluate the geometrical properties on mobility at the scaling limit.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Random discrete dopant induced variability in negative capacitance transistors 负电容晶体管中随机离散掺杂诱导的可变性
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354732
T. Dutta, V. Georgiev, A. Asenov
{"title":"Random discrete dopant induced variability in negative capacitance transistors","authors":"T. Dutta, V. Georgiev, A. Asenov","doi":"10.1109/ULIS.2018.8354732","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354732","url":null,"abstract":"In this work we investigate the impact of random discrete dopants (RDD) induced statistical variability in ferroelectric negative capacitance field effect transistors (NCFETs). We couple the 3D ‘atomistic’ statistical device simulator GARAND with the Landau — Khalatnikov equation of the ferroelectric for this study. We found that the negative capacitance effect provided by the ferroelectric layer can lead to suppression of the RDD induced variability in the threshold voltage (Vt), OFF-current (IOFF), and ON-current (ION). This immunity to RDD induced variability increases with increase in the ferroelectric thickness.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116767120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A flexible characterization methodology of RRAM: Application to the modelling of the conductivity changes and their variability RRAM的灵活表征方法:电导率变化及其可变性的建模应用
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354729
M. Pedró, J. Martín-Martínez, R. Rodríguez, M. Nafría
{"title":"A flexible characterization methodology of RRAM: Application to the modelling of the conductivity changes and their variability","authors":"M. Pedró, J. Martín-Martínez, R. Rodríguez, M. Nafría","doi":"10.1109/ULIS.2018.8354729","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354729","url":null,"abstract":"In this work, an automatic measurement setup, which allows a massive electrical characterization of RRAM with pulsed voltages, is presented. The evaluation of the G-V characteristics under single-pulse test-schemes is introduced as an example of application for neuromorphic engineering, where the fine analog control of the device conductivity state is required by inducing small changes in each iteration. To describe the obtained data, a time-independent compact model for memristive devices is used as inspiration. The model provided in the present work allows including device-level variability in the simulation, and considers the device electrical history. Both factors are key for further simulations of RRAM-based crossbar arrays, and the evaluation of the variability impact on their performance.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical characterization of HfO2 based resistive RAM devices having different bottom electrode metallizations 具有不同底电极金属化的HfO2基电阻性RAM器件的电学特性
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354734
S. B. Tekin Tubitak-Bilgem, S. Kalem Tubitak-Bilgem, Z. E. K. Tubitak-Bilgem, E. Jalaguier
{"title":"Electrical characterization of HfO2 based resistive RAM devices having different bottom electrode metallizations","authors":"S. B. Tekin Tubitak-Bilgem, S. Kalem Tubitak-Bilgem, Z. E. K. Tubitak-Bilgem, E. Jalaguier","doi":"10.1109/ULIS.2018.8354734","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354734","url":null,"abstract":"HfO2 based resistive RAM devices as the important candidates of future embedded non-volatile memory technology were investigated using state of art physical and electrical characterization methods. Memory stacks used for measurements, named MARS, having four different bottom electrode materials fabricated by CEA-LETI and ASM cooperation. The effects of bottom electrode metallization on Forming, switching and capacitive characteristics were studied and most efficient combinations were determined among these structures. It was observed that devices having atomic layer deposited (ALD) bottom electrode have some capacitive properties. Also TiN and TiWN bottom electrodes indicate promising switching characteristics and low operation voltages among others.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130856520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of TFET reverse currents into circuit operation: A case study TFET反向电流对电路运作的影响:个案研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354753
J. Núñez
{"title":"Impact of TFET reverse currents into circuit operation: A case study","authors":"J. Núñez","doi":"10.1109/ULIS.2018.8354753","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354753","url":null,"abstract":"Tunnel FET transistors (TFETs) are one of the most promising candidates to replace CMOS transistors for future integrated circuits. However TFET-based circuit design can exhibit significant limitations due to their reverse conduction currents caused by the direct bias of the intrinsic diode of these transistors. In this paper we analyze in depth this issue through the design of charge pump (DC-DC step up converters) circuits for energy harvesting applications. The proposed solution mitigates the impact of reverse conduction currents and, thus, improves power conversion efficiencies (PCE) compared to previous designs.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115272373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of SiGe channel introduction in FDSOI SRAM cell pFET and assessment of the Complementary-SRAM FDSOI SRAM单元fet中SiGe通道引入的研究及互补SRAM的评估
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354730
R. Berthelon, F. Andrieu, B. Giraud, O. Rozeau, O. Weber, F. Arnaud, M. Vinet
{"title":"Investigation of SiGe channel introduction in FDSOI SRAM cell pFET and assessment of the Complementary-SRAM","authors":"R. Berthelon, F. Andrieu, B. Giraud, O. Rozeau, O. Weber, F. Arnaud, M. Vinet","doi":"10.1109/ULIS.2018.8354730","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354730","url":null,"abstract":"In this work, we investigate the introduction of SiGe channel in FDSOI SRAM bitcells by the means of spice simulation. In classical SRAM configuration performance (read, write, retention) at a given leakage is only slightly impacted because of the SiGe stress partial relaxation in the small Pull-Up active dimensions. Since the SiGe compressive stress strongly enhances the hole mobility for long active stripes, it is relevant to design a so-called Complementary-SRAM bitcell, using SiGe pFETs as both Pull-Up and Pass-Gate devices. In such a configuration, the read current is enhanced by +21% with respect to the reference at the same leakage.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"325 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113998595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GDNMOS and GDBIMOS devices for ESD protection in 28nm thin film UTBB FD-SOI technology 用于ESD保护的GDNMOS和GDBIMOS器件采用28nm薄膜UTBB FD-SOI技术
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354737
L. De Conti, S. Cristoloveanu, M. Vinet, P. Galy
{"title":"GDNMOS and GDBIMOS devices for ESD protection in 28nm thin film UTBB FD-SOI technology","authors":"L. De Conti, S. Cristoloveanu, M. Vinet, P. Galy","doi":"10.1109/ULIS.2018.8354737","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354737","url":null,"abstract":"GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28nm thin film UTBB FD-SOI CMOS technology. Different connectivity conditions were measured and simulated. The devices are reconfigurable and promising for ESD protection applications.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127030197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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