Investigation of SiGe channel introduction in FDSOI SRAM cell pFET and assessment of the Complementary-SRAM

Abstract

In this work, we investigate the introduction of SiGe channel in FDSOI SRAM bitcells by the means of spice simulation. In classical SRAM configuration performance (read, write, retention) at a given leakage is only slightly impacted because of the SiGe stress partial relaxation in the small Pull-Up active dimensions. Since the SiGe compressive stress strongly enhances the hole mobility for long active stripes, it is relevant to design a so-called Complementary-SRAM bitcell, using SiGe pFETs as both Pull-Up and Pass-Gate devices. In such a configuration, the read current is enhanced by +21% with respect to the reference at the same leakage.