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2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)最新文献

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Cryogenic operation of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs Ω-gate p型绝缘体上硅基纳米线mosfet的低温运行
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354736
B. C. Paz, M. Pavanello, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot
{"title":"Cryogenic operation of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs","authors":"B. C. Paz, M. Pavanello, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot","doi":"10.1109/ULIS.2018.8354736","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354736","url":null,"abstract":"This work evaluates the operation of p-type Si0.7Ge0.3-on-insulator (SGOI) nanowires from room temperature down to 5.2K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Results show oscillations in both transconductance and gate to channel capacitance curves for temperatures smaller than 50K and fin width of 20nm due to quantum confinement effects. Improvement on the effective mobility for SGOI in comparison to SOI nanowires is still observed for devices with fin width scaled down to 20nm. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and SOI nanowires.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116120929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Ferroelectric properties of HfO2 interlayers in SOI and SOS pseudo-MOSFETs SOI和SOS伪mosfet中HfO2中间层的铁电特性
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354731
V. Popov, M. Ilnitsky, V. Antonov, V. Vdovin, I. Tyschenko, A. Miakonkikh, K. Rudenko
{"title":"Ferroelectric properties of HfO2 interlayers in SOI and SOS pseudo-MOSFETs","authors":"V. Popov, M. Ilnitsky, V. Antonov, V. Vdovin, I. Tyschenko, A. Miakonkikh, K. Rudenko","doi":"10.1109/ULIS.2018.8354731","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354731","url":null,"abstract":"Formation of a multi-crystalline HfO<inf>2</inf> film, containing ferroelectric phase OII (Pmn2<inf>1</inf>), after a high-temperature annealing at 1100°C, was experimentally observed for the first time in SOS structures obtained by a hydrogen transfer of silicon layer on Si or c-sapphire substrates respectively. PEALD HfO<inf>2</inf> interlayers with the thickness of 20 nm were deposited on silicon before bonding to reduce the defects and the magnitude of their charge at the SOI and SOS interfaces. SOS pseudo-MOS transistors demonstrate normal drain-gate characteristics with the charge carrier mobility as in bulk silicon and a smaller positive charge (≤ 1.2×10<sup>12</sup> cm<sup>−2</sup>). Moreover, a stable ferroelectric hysteresis with ΔV<inf>G</inf> ∼600 V promising for the embedded memory formation and they extend the functionality of logic circuits.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133920544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Innovative tunnel FET architectures 创新隧道场效应管架构
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354725
C. Llorente, S. Martinie, S. Cristoloveanu, J. Colinge, C. Le Royer, J. Wan, G. Ghibaudo, M. Vinet
{"title":"Innovative tunnel FET architectures","authors":"C. Llorente, S. Martinie, S. Cristoloveanu, J. Colinge, C. Le Royer, J. Wan, G. Ghibaudo, M. Vinet","doi":"10.1109/ULIS.2018.8354725","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354725","url":null,"abstract":"We propose three innovative SOI Tunnel FET architectures. They are evaluated and compared with a standard TFET structure using Sentaurus TCAD. The extension of the source (anode) at the bottom of the body generates vertical band-to-band tunneling with a very steep slope and higher ION than lateral tunneling, but only for gate lengths longer than 100 nm. Using a heavily doped boron thin layer at the bottom increases ION even for aggressive gate lengths. Implementation of a tip in the source provides performance similar to the reference TFET. TCAD simulation using SiGe instead of Si shows current drive increase when using the thin boron layer for very thin channels, even for shorter gate lengths.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121389313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Profiling border-traps by TCAD analysis of multifrequency CV-curves in Al2O3/InGaAs stacks Al2O3/InGaAs堆叠中多频cv曲线的TCAD分析
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354757
E. Caruso, J. Lin, K. F. Burke, K. Cherkaoui, D. Esseni, F. Gity, S. Monaghan, P. Palestra, P. Hurley, L. Selmi
{"title":"Profiling border-traps by TCAD analysis of multifrequency CV-curves in Al2O3/InGaAs stacks","authors":"E. Caruso, J. Lin, K. F. Burke, K. Cherkaoui, D. Esseni, F. Gity, S. Monaghan, P. Palestra, P. Hurley, L. Selmi","doi":"10.1109/ULIS.2018.8354757","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354757","url":null,"abstract":"This paper reports physics based TCAD simulations of multi-frequency C-V curves of In0.53Ga0.47As MOSCAPs including the AC response of the border traps. The calculations reproduce the experimental inversion and accumulation capacitance versus frequency, and provide a means to profile the space and energy density of states of border traps. A sensitivity analysis of the results to border traps' distribution is carried out changing the trap volume and the oxide capacitance.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131986801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The role of the bottom and top interfaces in the 1st reset operation in HfO2 based RRAM devices 在基于HfO2的RRAM设备中，底部和顶部接口在第一次复位操作中的作用
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354728
E. Pérez, M. K. Mahadevaiah, C. Zambelli, P. Olivo, C. Wenger
{"title":"The role of the bottom and top interfaces in the 1st reset operation in HfO2 based RRAM devices","authors":"E. Pérez, M. K. Mahadevaiah, C. Zambelli, P. Olivo, C. Wenger","doi":"10.1109/ULIS.2018.8354728","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354728","url":null,"abstract":"In this work, the increase on the conductive filament conductivity during the 1<sup>st</sup> Reset operation, by using the incremental step pulse with verify algorithm, in HfO<inf>2</inf> based 1T1R RRAM devices is investigated. A new approach is proposed in order to explain the increase of conductivity by highlighting the crucial roles played by both metal-oxide interfaces. The top metal-oxide interface (HfO<inf>2−x</inf>/Ti<inf>x</inf>O<inf>y</inf>) plays a crucial role in the forming operation by creating a strong gradient of oxygen vacancies in the hafnium oxide layer. The bottom metal-oxide interface (Ti<inf>x</inf>O<inf>y</inf>N<inf>z</inf>/HfO<inf>2−x</inf>) also creates oxygen vacancies, which strengthen the conductive filament tip near to this interface at the beginning of the 1<sup>st</sup> Reset, leading to the reported conductivity increase. After the 1<sup>st</sup> Reset operation the conductive filament stabilizes at the bottom interface suppressing this behavior in the subsequent reset operations.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124083334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Evaluation of thin-oxide Z2-FET DRAM cell 薄氧化Z2-FET DRAM电池的评价
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354342
S. Navarro, K. Lee, C. Márquez, C. Navarro, M. Parihar, H. Park, P. Galy, M. Bawedin, F. Gámiz, S. Cristoloveanu
{"title":"Evaluation of thin-oxide Z2-FET DRAM cell","authors":"S. Navarro, K. Lee, C. Márquez, C. Navarro, M. Parihar, H. Park, P. Galy, M. Bawedin, F. Gámiz, S. Cristoloveanu","doi":"10.1109/ULIS.2018.8354342","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354342","url":null,"abstract":"Advanced 28 nm node FDSOI Z2-FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Results demonstrate effective Z2-FET memory behavior for narrow devices (below 1 μm). As compared with thicker gate oxide Z2-FETs, thinning the insulator yields lower performance in terms of retention, variability and stability of the logic states during holding.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"35 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123520565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Unified feature scale model for etching in SF6 and Cl plasma chemistries SF6和Cl等离子体化学中蚀刻的统一特征比例模型
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354763
X. Klemenschits, S. Selberherr, L. Filipovic
{"title":"Unified feature scale model for etching in SF6 and Cl plasma chemistries","authors":"X. Klemenschits, S. Selberherr, L. Filipovic","doi":"10.1109/ULIS.2018.8354763","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354763","url":null,"abstract":"A novel unified feature-scale model for inductive plasma etching is presented. The semi-empirical model simplifies simulations by considering only surface reactions and ignoring those in the reactor. The model gives an accurate description of passivation layers which form on sidewalls during etch processes, by treating them as independent materials. This allows them to be explicitly included in subsequent etch steps, resulting in a more accurate description of the physical process. Therefore, novel gate stack geometries for advanced nodes can be modelled more rigorously, enabling a better understanding of the complex chemical and physical processes taking place during the gate stack etching sequence. The model was applied in the analysis of a gate stack geometry for CMOS devices of a 14nm process and compared to experimental results, which are in good agreement.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132489465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Computationally efficient analytic charge model for III-V cylindrical nanowire transistors III-V型圆柱纳米线晶体管的高效解析电荷模型
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354767
Mohit D. Ganeriwala, E. G. Marín, F. Ruiz, N. Mohapatra
{"title":"Computationally efficient analytic charge model for III-V cylindrical nanowire transistors","authors":"Mohit D. Ganeriwala, E. G. Marín, F. Ruiz, N. Mohapatra","doi":"10.1109/ULIS.2018.8354767","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354767","url":null,"abstract":"In this paper, we present a computationally efficient compact model for calculating the charges and gate capacitance of III-V cylindrical nanowire transistors. We proposed an approximation which decouples the Poisson and the Schrödinger equation and addresses the issues of developing a computationally efficient analytical model. Using the proposed approximation, we derived a model suitable for the circuit simulators. The model is physics based and does not include any empirical parameters. The accuracy of the model is verified across nanowires of different sizes and materials using simulation results from a 2D Poisson-Schrodinger solver.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"151 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131076991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Discussion on the 1/f noise behavior in Si gate-all-around nanowire MOSFETs at liquid helium temperatures 液态氦温度下硅栅全能纳米线mosfet 1/f噪声特性的讨论
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354739
D. Boudier, B. Crețu, E. Simoen, Anabela Veloso, N. Collaert
{"title":"Discussion on the 1/f noise behavior in Si gate-all-around nanowire MOSFETs at liquid helium temperatures","authors":"D. Boudier, B. Crețu, E. Simoen, Anabela Veloso, N. Collaert","doi":"10.1109/ULIS.2018.8354739","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354739","url":null,"abstract":"In this work, gate-all-around nanowire MOSFETs are studied at very low temperature (4.2 K) and drain voltage. It is shown that these conditions make quantum transport prevail over the usual drift diffusion mechanism. The 1/f noise level is investigated in order to study the impact of quantum transport on the noise mechanism. Generation-recombination noise shows the presence of traps in the gate oxide and in the silicon film. This work is completed by the low frequency noise spectroscopy analysis.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116365636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Scaling FDSOI technology down to 7 nm — A physical modeling study based on 3D phase-space subband boltzmann transport 缩放FDSOI技术至7纳米-基于三维相空间子带玻尔兹曼输运的物理建模研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI: 10.1109/ULIS.2018.8354741
Z. Stanojevic, O. Baumgartner, F. Schanovsky, G. Strof, C. Kernstock, M. Karner, J. Medina, F. Ruiz, A. Godoy, F. Gámiz
{"title":"Scaling FDSOI technology down to 7 nm — A physical modeling study based on 3D phase-space subband boltzmann transport","authors":"Z. Stanojevic, O. Baumgartner, F. Schanovsky, G. Strof, C. Kernstock, M. Karner, J. Medina, F. Ruiz, A. Godoy, F. Gámiz","doi":"10.1109/ULIS.2018.8354741","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354741","url":null,"abstract":"We present the first truly full-band approach to solving the subband Boltzmann transport (SBTE) equation in three-dimensional phase space. The solution is applied to investigate the evolution of the FDSOI MOSFET towards the 7nm node. Our findings show that single-gate FDSOI technology can be effectively scaled down to the 14 nm node, because the on-current gains are large enough to offset the SS-degradation. Beyond 14 nm a double-gate thin-body geometry is required to maintain electrostatic control.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114461023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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