{"title":"Unified feature scale model for etching in SF6 and Cl plasma chemistries","authors":"X. Klemenschits, S. Selberherr, L. Filipovic","doi":"10.1109/ULIS.2018.8354763","DOIUrl":null,"url":null,"abstract":"A novel unified feature-scale model for inductive plasma etching is presented. The semi-empirical model simplifies simulations by considering only surface reactions and ignoring those in the reactor. The model gives an accurate description of passivation layers which form on sidewalls during etch processes, by treating them as independent materials. This allows them to be explicitly included in subsequent etch steps, resulting in a more accurate description of the physical process. Therefore, novel gate stack geometries for advanced nodes can be modelled more rigorously, enabling a better understanding of the complex chemical and physical processes taking place during the gate stack etching sequence. The model was applied in the analysis of a gate stack geometry for CMOS devices of a 14nm process and compared to experimental results, which are in good agreement.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ULIS.2018.8354763","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A novel unified feature-scale model for inductive plasma etching is presented. The semi-empirical model simplifies simulations by considering only surface reactions and ignoring those in the reactor. The model gives an accurate description of passivation layers which form on sidewalls during etch processes, by treating them as independent materials. This allows them to be explicitly included in subsequent etch steps, resulting in a more accurate description of the physical process. Therefore, novel gate stack geometries for advanced nodes can be modelled more rigorously, enabling a better understanding of the complex chemical and physical processes taking place during the gate stack etching sequence. The model was applied in the analysis of a gate stack geometry for CMOS devices of a 14nm process and compared to experimental results, which are in good agreement.