S. Navarro, K. Lee, C. Márquez, C. Navarro, M. Parihar, H. Park, P. Galy, M. Bawedin, F. Gámiz, S. Cristoloveanu
{"title":"Evaluation of thin-oxide Z2-FET DRAM cell","authors":"S. Navarro, K. Lee, C. Márquez, C. Navarro, M. Parihar, H. Park, P. Galy, M. Bawedin, F. Gámiz, S. Cristoloveanu","doi":"10.1109/ULIS.2018.8354342","DOIUrl":null,"url":null,"abstract":"Advanced 28 nm node FDSOI Z2-FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Results demonstrate effective Z2-FET memory behavior for narrow devices (below 1 μm). As compared with thicker gate oxide Z2-FETs, thinning the insulator yields lower performance in terms of retention, variability and stability of the logic states during holding.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"35 14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ULIS.2018.8354342","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Advanced 28 nm node FDSOI Z2-FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Results demonstrate effective Z2-FET memory behavior for narrow devices (below 1 μm). As compared with thicker gate oxide Z2-FETs, thinning the insulator yields lower performance in terms of retention, variability and stability of the logic states during holding.