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2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)最新文献

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2D and 3D TCAD simulation of III-V channel FETs at the end of scaling 缩放结束时III-V沟道场效应管的二维和三维TCAD仿真
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354744
P. Aguirre, M. Rau, A. Schenk
{"title":"2D and 3D TCAD simulation of III-V channel FETs at the end of scaling","authors":"P. Aguirre, M. Rau, A. Schenk","doi":"10.1109/ULIS.2018.8354744","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354744","url":null,"abstract":"Quantum drift diffusion corrections and a simple ballistic mobility model are used to simulate IdVgs-characteristics of scaled 2D and 3D III-V channel FETs. The sub-threshold swing of double-gate ultra-thin-body geometries is extracted for different gate lengths, and the semi-classical results are compared with those from the quantum transport simulator QTx. The ballistic mobility recovers the QTx transfer curves of the gate-all-around nanowire FETs, except the on-currents in the linear regime. It is shown that source-to-drain tunneling sets a limit to scaling at a gate length of about 10 nm.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128106096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Z2-FET memory matrix in 28 nm FDSOI technology 28纳米FDSOI技术中的Z2-FET存储矩阵
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354341
M. Parihar, K. Lee, Hyung-Jin Park, C. Navarro, J. Lacord, F. Gámiz, P. Galy, S. Cristoloveanu, M. Bawedin
{"title":"Z2-FET memory matrix in 28 nm FDSOI technology","authors":"M. Parihar, K. Lee, Hyung-Jin Park, C. Navarro, J. Lacord, F. Gámiz, P. Galy, S. Cristoloveanu, M. Bawedin","doi":"10.1109/ULIS.2018.8354341","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354341","url":null,"abstract":"The article puts forth the comparison between the two available options of Z2-FET in 28 nm technological node, i.e. thin and thick gate-oxide. Thin gate-oxide technology favors the sense margin and scalability of dimensions and bias but suffers from higher gate leakage leading to poor retention and higher variability. On the other hand, thick-gate oxide device offers similar sense margin with long retention. TCAD mixed mode simulations show that Z2-RAM can be implemented successfully in the DRAM array with good performance metrics that can be further improved.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114661519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact of BOX thickness and ground-plane on non-linearity of UTBB FD-SOI MOS transistors BOX厚度和接地平面对UTBB FD-SOI MOS晶体管非线性的影响
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354769
Mandar S. Bhoir, N. Mohapatra
{"title":"Impact of BOX thickness and ground-plane on non-linearity of UTBB FD-SOI MOS transistors","authors":"Mandar S. Bhoir, N. Mohapatra","doi":"10.1109/ULIS.2018.8354769","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354769","url":null,"abstract":"This work investigates, for the first time, the impact of BOX thickness (Tbox) and Ground-plane (GP) on the non-linearity of transistors fabricated using UTBB FD-SOI CMOS technology. By extracting 2nd and 3rd order harmonic distortions, we have shown that the TBOX scaling and GP improve the transistor linearity at lower drain currents (low-power applications) in advanced FD-SOI technology nodes. The physics behind this observation i.e the additional mobility limiting factors, is explained in detail by using well calibrated TCAD simulations.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133897415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FoMPy: A figure of merit extraction tool for semiconductor device simulations 一个用于半导体器件模拟的价值提取工具
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354752
G. Espiñeira, N. Seoane, D. Nagy, G. Indalecio, A. García-Loureiro
{"title":"FoMPy: A figure of merit extraction tool for semiconductor device simulations","authors":"G. Espiñeira, N. Seoane, D. Nagy, G. Indalecio, A. García-Loureiro","doi":"10.1109/ULIS.2018.8354752","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354752","url":null,"abstract":"The aim of this work is to present an efficient tool that extracts the main figures of merit (FoM) of a semiconductors I-V curve and provides useful statistical parameters for variability studies. Two state-of-the-art devices have been used as benchmarks in order to show its capabilities. It includes several methods implemented to obtain the threshold voltage and allows the user to compare the results without compromising them by the methodology used. This study demonstrates the importance of choosing an appropriate method of extraction as the results may vary significantly thus making FoMPy an excellent tool to evaluate a device's performance.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121951634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
3D multi-subband ensemble Monte Carlo simulation of 〈100〉 and 〈110〉 Si nanowire FETs < 100 >和< 110 > Si纳米线场效应管的三维多子带集成蒙特卡罗模拟
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354724
L. Donetti, C. Sampedro, F. Ruiz, A. Godoy, F. Gámiz
{"title":"3D multi-subband ensemble Monte Carlo simulation of 〈100〉 and 〈110〉 Si nanowire FETs","authors":"L. Donetti, C. Sampedro, F. Ruiz, A. Godoy, F. Gámiz","doi":"10.1109/ULIS.2018.8354724","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354724","url":null,"abstract":"This work presents a comprehensive study of MOS transistors based on Si nanowires with 〈100〉 and 〈110〉 channel orientations employing our 3D Multi-Subband Ensemble Monte Carlo simulator. The results show that 〈100〉 oriented devices provide larger current and mobility than their 〈110〉 counterparts. The differences in the spatial charge distribution are analyzed and explained in terms of the population of the different valleys. Finally, a scaling analysis is performed, down to the channel length of 8nm. In this case, the differences observed between both orientations are minimal.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122122278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of electron effective mass variation on the performance of InAs/GaSb Electron-Hole Bilayer Tunneling Field-Effect Transistor 电子有效质量变化对InAs/GaSb电子-空穴双层隧道场效应晶体管性能的影响
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354755
J. Padilla, C. Medina-Bailón, M. Rupakula, C. Alper, C. Sampedro, F. Gámiz, A. Ionescu
{"title":"Impact of electron effective mass variation on the performance of InAs/GaSb Electron-Hole Bilayer Tunneling Field-Effect Transistor","authors":"J. Padilla, C. Medina-Bailón, M. Rupakula, C. Alper, C. Sampedro, F. Gámiz, A. Ionescu","doi":"10.1109/ULIS.2018.8354755","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354755","url":null,"abstract":"In the roadmap for the optimization of Electron-Hole Bilayer Tunneling Field-Effect Transistors (EHBTFETs), the employment of III-V compounds is regarded as an appealing solution due to their direct band-to-band tunneling injection. In order to achieve both n and p acceptable operation channels, the combination of As- and Sb-based III-V materials leads to the proposal of a heterosturcture InAs/GaSb-EHBTFET. In this paper, we analyze the impact that the required ultrathin InAs layers have on the electron effective mass and, subsequently, on the device performance.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131760440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Three p-silicon layers in reliable lateral double diffused metal oxide semiconductor transistor 可靠的横向双扩散金属氧化物半导体晶体管中的三个p-硅层
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354776
M. Mehrad
{"title":"Three p-silicon layers in reliable lateral double diffused metal oxide semiconductor transistor","authors":"M. Mehrad","doi":"10.1109/ULIS.2018.8354776","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354776","url":null,"abstract":"Inserting three p-layers in the drift region and buried oxide of the Lateral Double Diffused MOSFET (LDMOS) is the main goal of this paper. One of these layers is considered in the drift region and two others are in the buried oxide. Moreover, these layers have different lengths. The new structure helps to have high breakdown voltage and low on-resistance that improves Figure Of Merit (FOM) in this power transistor. Also, replacing p-silicon layer instead of silicon dioxide under the drift region reduces lattice temperature and helps to have a reliable device. The electrical parameters of the novel structure are compared with the conventional one using ATLAS simulator.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124967236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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