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2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)最新文献

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Energy harvesting power management circuit design in 22nm FDSOI technology 22nm FDSOI技术的能量收集电源管理电路设计
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354748
Z. Kaya, S. Tekin, S. Kalem
{"title":"Energy harvesting power management circuit design in 22nm FDSOI technology","authors":"Z. Kaya, S. Tekin, S. Kalem","doi":"10.1109/ULIS.2018.8354748","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354748","url":null,"abstract":"Today, users of existing commercial products expect longer battery life from the electronic products that they use in their daily activities. In addition to this, emerging technologies, especially in the Internet-of-Things domain require very long battery life time to be regarded as useful by their potential users. Energy harvesting methods which are used for extending the battery life or battery-free operation have been long studied by researchers. With the utilization of FD-SOI technology which can significantly reduce the leakage current in the stand-by mode of the electronic devices, more efficient energy harvesting power management integrated circuits can be designed. In this work, we present the design of an energy harvesting circuit which is optimized to benefit from the low leakage current characteristics of FD-SOI transistor.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"227 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132443298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multilevel parallelization approach to estimate spin lifetime in silicon: Performance analysis 在硅中估计自旋寿命的多级并行方法:性能分析
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354770
J. Ghosh, Dmitry Osintsev, V. Sverdlov, S. Ganguly
{"title":"Multilevel parallelization approach to estimate spin lifetime in silicon: Performance analysis","authors":"J. Ghosh, Dmitry Osintsev, V. Sverdlov, S. Ganguly","doi":"10.1109/ULIS.2018.8354770","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354770","url":null,"abstract":"Evaluation of the spin lifetime in thin Silicon films is a challenge because of the necessity of performing appropriate averaging of the strongly scattering momenta depending spin relaxation rates. Here we discuss a two-level highly parallelized algorithm to calculate the spin lifetime. This algorithm is based on a hybrid parallelization approach, using the message passing interface MPI as well as OpenMP. Most efficient way to maximally utilize the computational resources is described. Finally, how an application of shear strain can dramatically increase the spin lifetime is shown.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132756924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Finite element simulation of 2D percolating silicon-nanonet field-effect transistor 二维渗流硅纳米场效应晶体管的有限元模拟
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354760
T. Cazimajou, M. Mouis, G. Ghibaudo
{"title":"Finite element simulation of 2D percolating silicon-nanonet field-effect transistor","authors":"T. Cazimajou, M. Mouis, G. Ghibaudo","doi":"10.1109/ULIS.2018.8354760","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354760","url":null,"abstract":"Percolating networks of silicon nanowires, also called nanonets, have been proposed as a possible material for the channel of Field-Effect Transistors. Experimental results have shown that the dependence of current-voltage characteristics with parameters such as device dimension and nanowire density might be influenced by the statistical dispersion of individual nanowires threshold voltage. In order to further analyse this effect, this paper provides a finite element simulation of such nanonet-based field-effect transistor. We studied the influence on transistor characteristics of above-mentioned parameters. Simulation results were compared with experimental ones using the same parameter extraction methodology as in experiments.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"9 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120909639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Switching current reduction in advanced spin-orbit torque MRAM 先进自旋-轨道转矩MRAM开关电流减小
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354759
V. Sverdlov, A. Makarov, S. Selberherr
{"title":"Switching current reduction in advanced spin-orbit torque MRAM","authors":"V. Sverdlov, A. Makarov, S. Selberherr","doi":"10.1109/ULIS.2018.8354759","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354759","url":null,"abstract":"The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor (CMOS) devices. However, a rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to slow down this trend is to introduce non-volatility. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential to achieve these goals. It is particularly promising to employ non-volatility in IoT and automotive applications, as well as in the main computer memory as a replacement of conventional volatile CMOS-based DRAM. To further reduce the energy consumption, it is essential to replace SRAM in modern hierarchical multi-level processor memory structure with a non-volatile memory technology. The spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by relatively high switching currents. Several paths to reduce the switching current in an in-plane SOT-MRAM structure are analyzed. The switching by means of two orthogonal current pulses complemented with an interface-induced perpendicular magnetic anisotropy allows reducing the switching current significantly for achieving sub-500ps switching.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123370040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range 采用三栅无结mosfet解析紧凑模型，在宽温度范围内进行精确电路设计
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354743
A. Cerdeira, F. Avila-Herrera, M. Estrada, R. Doria, M. Pavanello
{"title":"Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range","authors":"A. Cerdeira, F. Avila-Herrera, M. Estrada, R. Doria, M. Pavanello","doi":"10.1109/ULIS.2018.8354743","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354743","url":null,"abstract":"This paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114413649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing 面向设计建模的28纳米FDSOI CMOS技术，低至4.2 K，适用于量子计算
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354742
A. Beckers, F. Jazaeri, H. Bohuslavskyi, L. Hutin, S. de Franceschi, C. Enz
{"title":"Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing","authors":"A. Beckers, F. Jazaeri, H. Bohuslavskyi, L. Hutin, S. de Franceschi, C. Enz","doi":"10.1109/ULIS.2018.8354742","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354742","url":null,"abstract":"In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121271557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A design-oriented charge-based simplified model for FDSOI MOSFETs 面向设计的FDSOI mosfet电荷简化模型
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354764
A. Pezzotta, F. Jazaeri, H. Bohuslavskyi, L. Hutin, C. Enz
{"title":"A design-oriented charge-based simplified model for FDSOI MOSFETs","authors":"A. Pezzotta, F. Jazaeri, H. Bohuslavskyi, L. Hutin, C. Enz","doi":"10.1109/ULIS.2018.8354764","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354764","url":null,"abstract":"In this paper a design-oriented model for asymmetrical double-gate (ADG) MOSFETs is proposed. Including the back-gate effect into the original simplified EKV bulk model requires only one additional parameter to the existing four, and extends the simplified EKV model to FDSOI processes. This will help the designer to find the right trade-off in terms of design parameters, including the back-gate biasing. A comparison with measurement results from a 28-nm FDSOI CMOS process is provided, assessing the excellent accuracy of the proposed.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121907179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Realization of vertical Ge nanowires for gate-all-around transistors 栅极全能晶体管用垂直锗纳米线的实现
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354771
M. Liu, K. Mertens, S. Glass, S. Mantl, D. Buca, Q. Zhao, S. Trellenkamp
{"title":"Realization of vertical Ge nanowires for gate-all-around transistors","authors":"M. Liu, K. Mertens, S. Glass, S. Mantl, D. Buca, Q. Zhao, S. Trellenkamp","doi":"10.1109/ULIS.2018.8354771","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354771","url":null,"abstract":"Towards gate-all-around (GAA) FETs, we present the top-down realization of vertical Ge nanowires (NWs) with defect-free sidewall and perfect anisotropy. The NW patterns are transferred by a novel inductively coupled plasma reactive ion etching (ICP-RIE) technique. With optimized etching conditions, sub-60 nm diameter Ge nanowires are guaranteed while mitigating micro-trenching and under-cutting effects. To further shrink the NW diameter, digital etching is followed including multiple cycles of self-limited O2 plasma oxidation and diluted HF rinsing. O2 plasma is also utilized for surface passivation in Ge MOScaps to improve the high-k/Ge interface. These NWs form the base of vertical transistors which are simulated by TCAD tools here. The processing techniques proposed in this work provide a viable option for low power vertical Ge and GeSn NW transistors.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121866079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Detailed analysis of frequency-dependent impedance in pseudo-MOSFET on thin SOI film SOI薄膜上伪mosfet频率阻抗的详细分析
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354774
S. Sato, Y. Omura, G. Ghibaudo, L. Benea, S. Cristoloveanu
{"title":"Detailed analysis of frequency-dependent impedance in pseudo-MOSFET on thin SOI film","authors":"S. Sato, Y. Omura, G. Ghibaudo, L. Benea, S. Cristoloveanu","doi":"10.1109/ULIS.2018.8354774","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354774","url":null,"abstract":"This paper reports detailed measurements of impedance in frequency domain and discusses the mechanisms affecting the ac response of pseudo-MOSFET method for SOI wafer with thin SOI film. The interplay between capacitance, channel resistance and contact resistance is demonstrated. Solutions for obtaining reliable C-V curves are proposed.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129573510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Inserting PN junction in a power device for achieving improved figure of merit 在功率器件中插入PN结，以提高性能因数
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354777
M. Zareiee, Hesam Salami
{"title":"Inserting PN junction in a power device for achieving improved figure of merit","authors":"M. Zareiee, Hesam Salami","doi":"10.1109/ULIS.2018.8354777","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354777","url":null,"abstract":"Lateral double diffused metal oxide semiconductor field effect transistors (LDMOS) in silicon on insulator (SOI) technology are widely applied in power applications. The breakdown voltage is high in these devices. In this paper a new LDMOS is presented to improve the performance achieving more reliable device. The idea is based on considering two silicon layers (P-type and N-type) in drift and insulator regions, respectively. The simulation with two dimensional ATLAS simulator shows that the breakdown voltage is increased. Moreover, the specific on-resistance and lattice temperature are improved. So, the Figure Of Merit (FOM) is significantly improved.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132022851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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