Switching current reduction in advanced spin-orbit torque MRAM

Abstract

The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor (CMOS) devices. However, a rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to slow down this trend is to introduce non-volatility. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential to achieve these goals. It is particularly promising to employ non-volatility in IoT and automotive applications, as well as in the main computer memory as a replacement of conventional volatile CMOS-based DRAM. To further reduce the energy consumption, it is essential to replace SRAM in modern hierarchical multi-level processor memory structure with a non-volatile memory technology. The spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by relatively high switching currents. Several paths to reduce the switching current in an in-plane SOT-MRAM structure are analyzed. The switching by means of two orthogonal current pulses complemented with an interface-induced perpendicular magnetic anisotropy allows reducing the switching current significantly for achieving sub-500ps switching.