采用三栅无结mosfet解析紧凑模型，在宽温度范围内进行精确电路设计

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI:10.1109/ULIS.2018.8354743

A. Cerdeira, F. Avila-Herrera, M. Estrada, R. Doria, M. Pavanello

{"title":"采用三栅无结mosfet解析紧凑模型，在宽温度范围内进行精确电路设计","authors":"A. Cerdeira, F. Avila-Herrera, M. Estrada, R. Doria, M. Pavanello","doi":"10.1109/ULIS.2018.8354743","DOIUrl":null,"url":null,"abstract":"This paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"276 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range\",\"authors\":\"A. Cerdeira, F. Avila-Herrera, M. Estrada, R. Doria, M. Pavanello\",\"doi\":\"10.1109/ULIS.2018.8354743\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.\",\"PeriodicalId\":383788,\"journal\":{\"name\":\"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)\",\"volume\":\"276 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ULIS.2018.8354743\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ULIS.2018.8354743","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文对所提出的紧凑的三栅无结纳米线晶体管解析模型进行了必要的调整，以便在宽温度范围内准确地描述器件的电特性。通过与实验结果的比较，验证了该模型在所有操作区域和温度下与连续电流及其导数的一致性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range

This paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

自引率

0.00%

发文量