Inserting PN junction in a power device for achieving improved figure of merit

Lateral double diffused metal oxide semiconductor field effect transistors (LDMOS) in silicon on insulator (SOI) technology are widely applied in power applications. The breakdown voltage is high in these devices. In this paper a new LDMOS is presented to improve the performance achieving more reliable device. The idea is based on considering two silicon layers (P-type and N-type) in drift and insulator regions, respectively. The simulation with two dimensional ATLAS simulator shows that the breakdown voltage is increased. Moreover, the specific on-resistance and lattice temperature are improved. So, the Figure Of Merit (FOM) is significantly improved.