缩放FDSOI技术至7纳米-基于三维相空间子带玻尔兹曼输运的物理建模研究

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-19 DOI:10.1109/ULIS.2018.8354741

Z. Stanojevic, O. Baumgartner, F. Schanovsky, G. Strof, C. Kernstock, M. Karner, J. Medina, F. Ruiz, A. Godoy, F. Gámiz

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引用次数: 1

摘要

我们提出了第一个真正的全带方法来解决三维相空间中的子带玻尔兹曼输运(SBTE)方程。该解决方案用于研究FDSOI MOSFET向7nm节点的演变。我们的研究结果表明，单门FDSOI技术可以有效地缩小到14 nm节点，因为导通电流增益足够大，可以抵消ss退化。在14nm以上，需要双栅极薄体几何结构来保持静电控制。

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Scaling FDSOI technology down to 7 nm — A physical modeling study based on 3D phase-space subband boltzmann transport

We present the first truly full-band approach to solving the subband Boltzmann transport (SBTE) equation in three-dimensional phase space. The solution is applied to investigate the evolution of the FDSOI MOSFET towards the 7nm node. Our findings show that single-gate FDSOI technology can be effectively scaled down to the 14 nm node, because the on-current gains are large enough to offset the SS-degradation. Beyond 14 nm a double-gate thin-body geometry is required to maintain electrostatic control.

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2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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