基于共掺杂si - nc的MIS结构中电压或电流充电脉冲偏置的记忆效应研究

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI:10.1109/ULIS.2018.8354749

A. Mazurak, Jakub Jasmski, R. Mroczyński

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引用次数: 0

摘要

共掺杂Si-NCs已被引入到具有HfOx栅介电层的MIS结构中。制备的测试结构通过应力和传感器测量来表征器件电容、平带电压位移和保持时间。本文的研究结果对Si-NCs在存储结构中的应用具有重要意义。

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Investigation of memory effect with voltage or current charging pulse bias in MIS structures based on codoped Si-NCs

Co-doped Si-NCs have been introduced into MIS structures with HfOx gate dielectric layers. The fabricated test structures were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Presented results are promising for applications of Si-NCs in memory structures.

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来源期刊

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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