发布求助
文献互助 智能选刊 最新文献

30th European Solid-State Device Research Conference最新文献

筛选
英文 中文
Scalable Inductor Model on Lossy Substrates with Accurate Eddy Current Simulation 损耗基板上可扩展电感模型及精确涡流模拟
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194739
M. Peter, P. Baureis, H. Hein, F. Oehler
{"title":"Scalable Inductor Model on Lossy Substrates with Accurate Eddy Current Simulation","authors":"M. Peter, P. Baureis, H. Hein, F. Oehler","doi":"10.1109/ESSDERC.2000.194739","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194739","url":null,"abstract":"The model developed in this work is especially designed for epi-layer substrates with highly conductive bulk-substrates of typically 0.01Ωcm. Eddy currents play a major role and their effects are therefore accurately modeled. This is done by simulating the current distribution in the substrate and then fitting monomial equations to the results. The resulting model is scalable and does not need any fitting to measurements. The circuit describing the model is compact, which makes it easy to implement it in standard design tools. Excellent agreement to measurements is found for a wide range of inductors.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131609481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Shallow and Deep Trench Isolation for use in RF-Bipolar IC:s 用于rf双极IC的浅沟槽和深沟槽隔离
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194752
M. Forsberg, C. Bormander, T. Johansson, T. Ko, W. Liu, M. Vellaikal, A. Cheshire
{"title":"Shallow and Deep Trench Isolation for use in RF-Bipolar IC:s","authors":"M. Forsberg, C. Bormander, T. Johansson, T. Ko, W. Liu, M. Vellaikal, A. Cheshire","doi":"10.1109/ESSDERC.2000.194752","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194752","url":null,"abstract":"A novel self-aligned shallow and deep trench isolation for bipolar or BiCMOS RF-IC:s, using both Poly and STI CMP steps for excellent planarity, is presented. The concept is described and verified using a 0.25 μm, 200 mm bipolar epi-base RF process. Process data, SEM micrographs and electrical data are used to verify the validity of the concept.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133056677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Novel Functional Negative-Differential-Resistance Heterojunction Bipolar Transistor (NDR-HBT) 新型功能负微分电阻异质结双极晶体管(NDR-HBT)
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194760
W. Liu, W.C. Wang, H. Pan, C. Cheng, S. Feng, C. Yen, K.W. Lin
{"title":"A Novel Functional Negative-Differential-Resistance Heterojunction Bipolar Transistor (NDR-HBT)","authors":"W. Liu, W.C. Wang, H. Pan, C. Cheng, S. Feng, C. Yen, K.W. Lin","doi":"10.1109/ESSDERC.2000.194760","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194760","url":null,"abstract":"A novel functional negative-differentialresistance heterojunction bipolar transistor (NDR-HBT) has been successfully fabricated and demonstrated. The studied device acts as a conventional HBT for the applied higher base current of IB=100μA/step. However, the NDR phenomenon with interesting topee-shaped current-voltage characteristics was observed under the applied base current of IB=2μA/step. These are attributed to the use of narrow base width and δ-doped sheet in the studied device. Besides, the N-shaped NDR phenomena are obviously observed under the applied tungsten light source. The peak-to-valley current ratio (PVCR) up to 1.5 is obtained for the base current IB=60μA. The photocurrent is about 1.01mA and keeps constantly under the applied higher base current.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133845391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Channel Noise Current in Deep Sub-Micron MOSFETs 深亚微米mosfet的通道噪声电流
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194826
Chih-Hung Chen, M. Jamal Deen, M. Matloubian, Yuhua Cheng
{"title":"Channel Noise Current in Deep Sub-Micron MOSFETs","authors":"Chih-Hung Chen, M. Jamal Deen, M. Matloubian, Yuhua Cheng","doi":"10.1109/ESSDERC.2000.194826","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194826","url":null,"abstract":"An extraction method to obtain the channel noise current in deep-submicron MOSFETs directly from DC, scattering parameter and RF noise measurements is presented. Extracted channel thermal noise from long channel devices is consistent with the long channel theory (id 2/∆f = γ 4kTgdo with γ =2/3 in saturation). The value of γ can increase up to 1.3 for a 0.18μm device. Extracted channel thermal noise as a function of bias for five different channel lengths is also presented.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125757803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Role of interface and bulk defect-states in the low-voltage leakage conduction of ultrathin oxides 界面和本体缺陷态在超薄氧化物低压漏导中的作用
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194777
D. Ielmini, A. Spinelli, A. Lacaita, G. Ghidini
{"title":"Role of interface and bulk defect-states in the low-voltage leakage conduction of ultrathin oxides","authors":"D. Ielmini, A. Spinelli, A. Lacaita, G. Ghidini","doi":"10.1109/ESSDERC.2000.194777","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194777","url":null,"abstract":"Experimental results on the leakage effects in ultrathin oxides ( nm) reveal that electron-hole recombination dominates the conduction process, at least at low voltages. The dependences of leakage and interface states on stress dose, stress polarity and time after stress are analyzed, providing evidence for the dominant role of bulk defect states in the leakage mechanism. Simulations with a recombinationand trapassisted tunneling model are finally shown, in support of the interpretation based on bulk defects.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
2D dopant profiling of advanced CMOS technologies by preferential etching, comparison with 2D process simulations 基于优先蚀刻的先进CMOS技术的二维掺杂谱，与二维工艺模拟的比较
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194789
C. Dachs, M. Verheijen, M. Kaiser, P. Stolk, Y. Ponomarev
{"title":"2D dopant profiling of advanced CMOS technologies by preferential etching, comparison with 2D process simulations","authors":"C. Dachs, M. Verheijen, M. Kaiser, P. Stolk, Y. Ponomarev","doi":"10.1109/ESSDERC.2000.194789","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194789","url":null,"abstract":"In this paper the possibilities for quantitative determination of 2D dope profiles in advanced CMOS technologies are investigated using selective etching in combination with TEM, SIMS and AFM. Promising results were obtained for As. For B an etch-rate dependence on the steepness of the B concentration gradient and influence of the background channel doping (As and P) seem to trouble quantification. A comparison between the measured and simulated (TSUPREM4) 2D profile of a 0.18μm NMOST is presented.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129869650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Physically Based Comparison of Current Noise Analysis of Si BJT's and SiGe HBT's 基于物理的Si BJT和SiGe HBT电流噪声分析比较
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194736
M. Martin-Martinez, D. Pardo
{"title":"Physically Based Comparison of Current Noise Analysis of Si BJT's and SiGe HBT's","authors":"M. Martin-Martinez, D. Pardo","doi":"10.1109/ESSDERC.2000.194736","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194736","url":null,"abstract":"We present the first physically based conclusions of noise reduction in a HBT as compared with an identical BJT, based on the direct comparison of emitter, base and collector current fluctuations. In the HBT (as compared to the BJT), the largest reduction of the RF values of the spectral density of current fluctuations derives from the SJB and the SJBJE terms (22 % and 31 %, respectively). This is due to the fact that the base current in the HBT (mainly formed by holes crossing to the emitter) is strongly reduced as a consequence of the lower gap of the SiGe base. When studying the dc dependence of the different noise spectra, SJE(0), SJC(0) and SJEJC(0) undergo a pronounced rise in BJT and HBT as JC increases. However, the SJB(0) term can be neglected in the total noise analysis in the HBT for lower values of JC.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129889729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Subthreshold hump mechanisms for both surface and buried channel MOSFET using STI technology 基于STI技术的表面沟道和埋地沟道MOSFET的阈下驼峰机制
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194726
Hsin-Yi Lee, Chih-Sheng Chang, T. Hsieh, Jyh-Chyurn Guo
{"title":"Subthreshold hump mechanisms for both surface and buried channel MOSFET using STI technology","authors":"Hsin-Yi Lee, Chih-Sheng Chang, T. Hsieh, Jyh-Chyurn Guo","doi":"10.1109/ESSDERC.2000.194726","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194726","url":null,"abstract":"The fundamental differences between buried-channel (BC) and surface-channel (SC) devices adopting shallow trench isolation (STI) technology are studied by using silicon data and 2D process/device simulation. For wafers with intentionally enhanced STI divots, the well-known STI induced double-hump is extensively observed for SC NMOS devices. However, BC PMOS devices keep from double-hump for all splits. The 2D simulation contours reveal that for BC PMOS devices, the corner filed crowding accelerates the depletion of holes in the BC near the STI top corner. Furthermore, the worsen segregation of counter-doped impurities near STI top corner leads to a higher magnitude of local threshold voltage associated with the corner devices.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128711054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Global Self-Heating Model for Device Simulation 器件仿真的全局自热模型
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194780
T. Grasser, R. Quay, V. Palankovski, S. Selberherr
{"title":"A Global Self-Heating Model for Device Simulation","authors":"T. Grasser, R. Quay, V. Palankovski, S. Selberherr","doi":"10.1109/ESSDERC.2000.194780","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194780","url":null,"abstract":"For the design and simulation of many state-of-the-art devices self-heating effects must be considered. This is a very difficult task as thermal effects are basically threedimensional effects which can not as easily be reduced to two-dimensions as it is possible for many purely electrical problems. Furthermore, the thermal active volume is much larger than the electrical area and the thermal boundary conditions are difficult to measure. We propose a global self-heating model which is capable of accurate consideration of thermal effects and is because of its computational efficiency and robustness sometimes even better suited for some problems than the solution of the standard lattice","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electrical characterisation of n and p-channel SiGe MOSFETs with gate oxides formed by plasma oxidation 用等离子体氧化形成栅氧化物的n沟道和p沟道SiGe mosfet的电学特性
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194809
L. Riley, S. Hall, J. Zhang, B. Gallas, A. Evans
{"title":"Electrical characterisation of n and p-channel SiGe MOSFETs with gate oxides formed by plasma oxidation","authors":"L. Riley, S. Hall, J. Zhang, B. Gallas, A. Evans","doi":"10.1109/ESSDERC.2000.194809","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194809","url":null,"abstract":"Surface channel strained SiGe MOSFETs have been fabricated using a low thermal budget process including gate oxidation by plasma anodisation at circa 100C. The fabrication process is detailed together with electrical characterisation of n and plong channel mosfets and the first 0.1μm LDD SiGe nMOSFETs. Limited increased mobilities for buried channel transistors and reduced ones for surface channel mosfets are apparent.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130030646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信