30th European Solid-State Device Research Conference最新文献

{"title":"The influence of silicon interstitial clusters on the Reverse Short Channel Effect","authors":"C. Tsamis, D. Tsoukalas, A. Tserepi, E. Tsoi","doi":"10.1109/ESSDERC.2000.194742","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194742","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance 0.1 um pMOSFETs with optimized poly-Si and poly-SiGe gates","authors":"E. Josse, T. Skotnicki, M. Jurczak, F. Martin, M. Paoli, B. Tormen, C. Hernandez, I. Campidelli","doi":"10.1109/ESSDERC.2000.194836","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194836","url":null,"abstract":"In this paper, we demonstrate that a careful optimization of poly-Si and polySiGe gates is able to extend these materials validity, thus postponing the need for metal gate. Improving dopant drive-in and interfacial distribution with fine-grain columnar poly-Si or increasing interfacial activation with poly-SiGe drastically reduces gate poly depletion and helps in suppressing B penetration. Using these options, we show highly performant 0.12 and 0.10 μm pMOS at 1.5V and 1.2V, with drive current as high as 350 μA/μm for IOFF=1 nA/μm and 300μA/μm for IOFF=25 nA/μm, respectively.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121113385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PLEDs for Integration with MOS Circuits","authors":"L. Heinrich, J. Horstmann, K. Goser","doi":"10.1109/ESSDERC.2000.194848","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194848","url":null,"abstract":"A new promising way for the monolithic integration of light emitting devices on the top of MOS circuits is discribed. The active layer consists of PPV or MeLPPP light emitting polymer material (LEP) with an ITO cathode and a metallic anode. All process steps, including the possibility of dry etching of the active layer and structuration of the upper electrode, are typical for MOS-technology. Currentvoltage and current-intensity measurements of the devices are done for characterisation. These polymeric light emitting diodes (PLED) allow the monolithic integration of MOS microelectronic circuits and light emitting devices on a silicon chip forming one","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123221570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Voltage MOS Transistor with a Folded n- Region for Flash Technology","authors":"F. Hofmann, W. Rosner, E. Landgraf","doi":"10.1109/ESSDERC.2000.194757","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194757","url":null,"abstract":"Floating gate devices like EEPROM and Flash memory require high voltages up to 20 V for programming and erase operations. This high voltage can only be handled with large MOS transistors. A common approach is to form a drift region which increases the on-resistance of the transistor. Here an extra voltage drop between the contact and the transistor channel is gernerated. In order to save chip area, a transistor is presented with the high resistive drift regions folded into the trenches on both sides of the gate.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116457989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scalable High Voltage Trenchgate Transistor for Flash","authors":"E. Landgraf, F. Hofmann, H. von Philipsborn","doi":"10.1109/ESSDERC.2000.194794","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194794","url":null,"abstract":"A trench-gate n-MOSFET suitable for high voltage operation as required for flash memories or LCD-Displays is studied. The transistor channel is folded into the substrate along the walls of a trench. This geometry offers area scalability while keeping minimum dimensions of channel length and ldd drift region needed to deal with the high voltages. The maximum drain voltage of 15V for the transistors examined is limited by breakdown of the reverse biased drainsubstrate junction. Short channel effects as DIBL or punchthrough are suppressed due to the concave corner effect for structures down to 0.6 m gate footprint.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122343093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient I-V-Characteristics of OLEDs with Deep Traps","authors":"S. Scheinert, G. Paasch, P. Nguyen, S. Berleb, W. Brutting","doi":"10.1109/ESSDERC.2000.194810","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194810","url":null,"abstract":"Measured current-voltage-characteristics of OLEDs show a large hysteresis for different sweep directions. To clarified this peculiarity we have carried out 2D simulations of transient current-voltage characteristics with a systematic variation of the relevant parameters to investigate this characteristics. It turns out that the transient behaviour can be explained by deep traps. Due to the high energy gap of organic materials deep traps can lie far from the bands. Further, the thermal velocity of the carriers is extremely low and consequently the time constant for trap recharging is very high. Therefore, a high delay time is necessary to measure the reverse steady-state current and to prevent the hysteresis effects.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122917077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Technology and System Integration of CMOS Image Sensors","authors":"J. Holz, I. Koren, U. Ramacher","doi":"10.1109/ESSDERC.2000.194724","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194724","url":null,"abstract":"The major drawback of the CMOS image sensors when compared to CCD devices is reduced image quality at low illumination due to lower quantum efficiency and larger leakage current of the CMOS photodiodes. In this paper, a novel photodiode structure is presented. Only minor changes to the original CMOS process were applied that don't affect the parameters of other devices. The quantum efficiency of the novel photodiode was nearly doubled and the leakage current was decreased by almost 2 orders of magnitude with respect to a source/drain junction photodiode. The concept is expected to be also applicable to future CMOS processes. This makes the benefits of the system integration of sensor and signal processing on a single CMOS chip available to applications requiring good image quality at low-light levels.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128392224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Atomistic Insights into Ultra-Shallow Junction Formation","authors":"P. Griffin","doi":"10.1109/ESSDERC.2000.194718","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194718","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124064440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process","authors":"J. Mitros, C. Tsai, Hisashi Shichijo, Keith Edmund Kunz, A. Morton, D. Goodpaster, D. Mosher, T. Efland","doi":"10.1109/ESSDERC.2000.194793","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194793","url":null,"abstract":"Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no cost adder.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125729888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent Progress on Advanced Interconnects","authors":"M. Moussavi","doi":"10.1109/ESSDERC.2000.194720","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194720","url":null,"abstract":"This paper gives an overview of the international state of the art to overcome critical issues of advanced interconnects. Introduction Prior to the most challenging solutions on optical interconnects, IC makers have to find viable processes and materials for short and mid term requirements. For the resistivity requirement of 2.2 μΩ.cm (sum of barrier and metal resistivities) copper has been chosen to be integrated in a damascene architecture. The interlevel metal insulator effective dielectric constant requirement in the range of 1.5 to 2 can be achieved by using porous silica. The following sections will describe, step by step, critical issues in the integration of these materials with reference to the recent publications. Interconnect schemes analysis In this section, we present RC analysis only with material change. The dimensions (metal width and space) for each generation correspond to the minimum requirements of the ITRS. Effective (barrier and metal) resistivity of 3.5 μΩ.cm for Al and 2.2 μΩ.cm for Cu have been chosen. Finally, the metal height remains constant from one design rule to another. This model gives simulation results presented in figure 1. These results show clearly that from 0.25 μm to 0.1 μm, substitution of Al by Cu and SiO2 by k=3 and k=2 dielectric materials keeps quasi constant the RC, while unchanged combination of metal and dielectric, drastically increases the parasitics in the following generation. For Cu based interconnects, dual Damascene architecture is adopted using different strategies which are classified in two categories (self aligned and not self aligned structures). Figures 2-5 show 2 examples of fabrication steps and their related SEM views: i) Via first at via level as a self aligned structure ii) Via first at trench level as a not self aligned one. In both examples, absence of shift between lines and vias lead to a well defined structure. In case of misalignments, the self aligned strategy allows reduced via size and as designed meat space while the second strategy gives a reduced metal space and as designed via size. Technological issues Ebeam lithography has been used for extremely narrow geometries with available negative photo resists. Recent significant progress on 193 nm lithography demonstrates the possibility of DUV techniques for 0.12 μm generation as illustrated in figure 6. To verify the results predicted by the simulation model, one has to fabricate a multilevel interconnect structure with new materials. Different steps with potential issues are listed below: • Low k dielectric ⇒ Effective dielectric constant, adhesion, moisture absorption, mechanical and thermal stability, chemical compatibility with different reactants, heat dissipation Concerning isolation, the material impact on total capacitance and thermal conductivity is summarized in figure 7. The total capacitance has been measured with inter metal line low k and inter layer SiO2. Xerogel dielectrics (k=2.4) allow close to 50% reduct","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134575187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}