Recent Progress on Advanced Interconnects

Abstract

This paper gives an overview of the international state of the art to overcome critical issues of advanced interconnects. Introduction Prior to the most challenging solutions on optical interconnects, IC makers have to find viable processes and materials for short and mid term requirements. For the resistivity requirement of 2.2 μΩ.cm (sum of barrier and metal resistivities) copper has been chosen to be integrated in a damascene architecture. The interlevel metal insulator effective dielectric constant requirement in the range of 1.5 to 2 can be achieved by using porous silica. The following sections will describe, step by step, critical issues in the integration of these materials with reference to the recent publications. Interconnect schemes analysis In this section, we present RC analysis only with material change. The dimensions (metal width and space) for each generation correspond to the minimum requirements of the ITRS. Effective (barrier and metal) resistivity of 3.5 μΩ.cm for Al and 2.2 μΩ.cm for Cu have been chosen. Finally, the metal height remains constant from one design rule to another. This model gives simulation results presented in figure 1. These results show clearly that from 0.25 μm to 0.1 μm, substitution of Al by Cu and SiO2 by k=3 and k=2 dielectric materials keeps quasi constant the RC, while unchanged combination of metal and dielectric, drastically increases the parasitics in the following generation. For Cu based interconnects, dual Damascene architecture is adopted using different strategies which are classified in two categories (self aligned and not self aligned structures). Figures 2-5 show 2 examples of fabrication steps and their related SEM views: i) Via first at via level as a self aligned structure ii) Via first at trench level as a not self aligned one. In both examples, absence of shift between lines and vias lead to a well defined structure. In case of misalignments, the self aligned strategy allows reduced via size and as designed meat space while the second strategy gives a reduced metal space and as designed via size. Technological issues Ebeam lithography has been used for extremely narrow geometries with available negative photo resists. Recent significant progress on 193 nm lithography demonstrates the possibility of DUV techniques for 0.12 μm generation as illustrated in figure 6. To verify the results predicted by the simulation model, one has to fabricate a multilevel interconnect structure with new materials. Different steps with potential issues are listed below: • Low k dielectric ⇒ Effective dielectric constant, adhesion, moisture absorption, mechanical and thermal stability, chemical compatibility with different reactants, heat dissipation Concerning isolation, the material impact on total capacitance and thermal conductivity is summarized in figure 7. The total capacitance has been measured with inter metal line low k and inter layer SiO2. Xerogel dielectrics (k=2.4) allow close to 50% reduction of the capacitance but it's thermal conductivity is 10 times smaller than SiO2 which may cause reliability issues. • Dielectric etching and stripping (after lithography) ⇒ Trench and via profiles, compatibility of strippers with low k materials, Cu cleaning (via) The etching of low k materials can be quite challenging as described by Bell labs (1). Fluorocarbon chemistries with high bias power is commonly used to disrupt the strong Si-O bonds, whereas in the case of a pure organic dielectric, as SilK material for example, the active etchant is oxygen. Conventional dilute HF process is efficient for sidewall Cu contamination cleaning. However, CD loss can not be avoided. In addition, due to the relative porosity of advanced low k materials, new cleaning chemistries have to be developed for resist stripping at hard mask level (2). • Diffusion barrier deposition ⇒ Conformality, barrier resistivity and performance versus thickness, adhesion to Cu and the underneath dielectric. New barrier studies suitable for more aggressive features are focused on CVD WxN (3) or TaN (4) and Electrolessly deposited Co(P) or Ni(P) (5). However, the integration capability of these materials for below 0.18 μm geometries has to be demonstrated. For example, the minimum thickness for which barrier performance data of electroless Co(P) material are available is 50 nm. As shown in figure 8, effective resistivity of 2.2 μΩ.cm can be obtained either by decreasing drastically the thickness of a 200μΩ.cm barrier (down to 7 nm for 0.1 μm metal width) or select a 8 nm thick of a 30 μΩ.cm barrier. For the line level, the thickness impact is much more important than the resistivity value. • Cu deposition ⇒ Conformality (filling capability of new techniques), adhesion and purity of the films due to CVD precursors or intensive use of additives in electroplating chemistries. The issue of filling small features can be addressed in the case of superconformal or bottom-up Cu filling (6). • Cu CMP ⇒ Process compatibility with low k/barrier/Cu stack in terms of mechanical and chemical stability As reported by Sematech (7), polishing xerogel damascene structures is difficult due to the poor mechanical strength of the film and necessitate the deposition of both conformal oxide liner (at line level and after etch) and capping layer. Electrical Results: State of the art In this section we give some integration examples including comparative electrical results in terms of RC reduction with different metal/dielectric combinations. Our simulation model presented in the first section, has been validated by experimental reduction of 40% of the RC between Cu/Silk and Cu/SiO2 for 0.18 μm double level metal interconnect (8). IBM presented recently (9) third metal capacitance comparison between various metal/dielectric combinations. For the minimum pitch of 0.63 μm and constant line resistance, Cu/FSG results in a 10% reduction in total RC delay relative to Al/FSG case or Cu/HSG (figure 9). Using Flare material (k=2.8), more than 30% reduction of wiring capacitance was obtained for 0.24/0.24 μm line/space in comparison with TEOS dielectric (Matsushita (10)). Lower permittivity values can be obtained with porous silica. Sematech has already reported Cu/xerogel integration (7) (figures 10-11). Finally the ultimate k=1 value is achievable with air gap structures. Figure 13 shows SEM cross section of a 2 level metallization based on SiOC/Airgap structure reported by our group (11). The comparison of this new interconnect scheme with Cu/SiO2, shows that the SiOCAirGap dielectric leads to a 55% improvement of the interconnect total capacitance, for a 0.32μm metal space. Conclusion Many difficult challenges coming from new material introduction for advanced interconnects can be addressed as shown by several Multilayer interconnects results in the literature. Further improvements concern etching profile of low k materials as well as barrier thickness reduction in favor of a void free, low resistance metal lines and vias. Even with optimized process steps, without relaxing the pitch, RC can only be kept constant if one material is changed from one generation to another. This is a severe constraint for research and development and also for future production since technology qualification is requiring extensive efforts of physical, electrical and reliability characterizations.