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Simple Formulae for the Effective Plus-Factor for Transient Enhanced Diffusion 瞬态增强扩散有效附加因子的简单公式
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194741
G. Hobler, V. Moroz
{"title":"Simple Formulae for the Effective Plus-Factor for Transient Enhanced Diffusion","authors":"G. Hobler, V. Moroz","doi":"10.1109/ESSDERC.2000.194741","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194741","url":null,"abstract":"Simple analytical expressions for the effective plus-factor for transient enhanced diffusion after non-amorphizing implantations in silicon are presented. The formulae describe the ion mass, implant energy, and dose dependence of the numerically calculated plus-factor with a root mean square error of 3%. The accuracy of the numerical data as well as possible errors from a depth dependence of the plus-factor are dis-","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125703640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cathode Hot Electrons and Anode Hot Holes in Tunneling MOS Capacitors 隧道MOS电容器的阴极热电子和阳极热孔
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194773
P. Palestri, L. Selmi, E. Sangiorgi, M. Pavesi, F. Widdershoven
{"title":"Cathode Hot Electrons and Anode Hot Holes in Tunneling MOS Capacitors","authors":"P. Palestri, L. Selmi, E. Sangiorgi, M. Pavesi, F. Widdershoven","doi":"10.1109/ESSDERC.2000.194773","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194773","url":null,"abstract":"This paper presents simulations of electron and hole gate currents in thin oxide tunneling MOS capacitors, based on a newly developed Monte Carlo code for Si-SiO Si stacks. Fully bipolar simulations with state of the art Si and SiO transport models predict a previously neglected population of cathode hot electrons proportional to that of the anode hot holes, often regarded as responsible of oxide degradation. The bias dependence of this population is discussed in view of recently reported results on the role of hole injection and transport in device degradation.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131241461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Analysis on the Avalanche Ruggedness of Finger Type and Stripe Type LDMOS Transistor 手指型和条纹型LDMOS晶体管的雪崩耐用性分析
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194758
T. Kwon, Y.C. Choi, C.J. Kim, H. Kang, C.S. Song
{"title":"Analysis on the Avalanche Ruggedness of Finger Type and Stripe Type LDMOS Transistor","authors":"T. Kwon, Y.C. Choi, C.J. Kim, H. Kang, C.S. Song","doi":"10.1109/ESSDERC.2000.194758","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194758","url":null,"abstract":"In order to investigate how to change avalanche ruggedness according to layout type in LDMOS, the two types of structure such as finger type and stripe type were investigated. The difference of the avalanche ruggedness is due to inductor voltage difference caused by body-pinch resistance and the inductor voltage difference affects the ratio of Emax (reverse maximum holding energy of device) variation to load inductance (L) variation (= Emax / L). In this paper, we describe in detail how to optimize the layout type of LDMOS according to their load inductance (L).","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121905154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quantum Effects in SOI Single-Hole Transistors SOI单孔晶体管中的量子效应
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194754
X. Tang, X. Baie, J. Colinge, F. van de Wiele, V. Bayot
{"title":"Quantum Effects in SOI Single-Hole Transistors","authors":"X. Tang, X. Baie, J. Colinge, F. van de Wiele, V. Bayot","doi":"10.1109/ESSDERC.2000.194754","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194754","url":null,"abstract":"SOI single-hole transistors with various sizes have been fabricated by converting an abacus bead wire to an island contacted to the source and the drain through two constrictions. Coulomb blockade and quantum confinement oscillations have been observed in these devices; The energy spectrum in the different regions and the energy levels in the constrictions as a function of the gate voltage have been calculated solving Poisson and Schrodinger equations self-consistently. The ground-state energy of the hole in the constrictions is lower than in the island, thereby creating a potential barrier.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121956933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-consistent Optimization and Performance Analysis of Double-Gate MOS Transistors 双栅MOS晶体管自洽优化及性能分析
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194783
S. Monfray, J. Autran, M. Jurczak, T. Skotnicki
{"title":"Self-consistent Optimization and Performance Analysis of Double-Gate MOS Transistors","authors":"S. Monfray, J. Autran, M. Jurczak, T. Skotnicki","doi":"10.1109/ESSDERC.2000.194783","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194783","url":null,"abstract":"The influence of architecture parameters on the charge carrier concentration has been theoretically investigated in both p-channel and n-channel Double Gate MOSFET’s. Based on a self-consistent solving of the Schrödinger and Poisson equations, this work clearly shows and quantifies the importance of the silicon thin-film thickness for electrical performance optimization of the device.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115331705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploring Various MOS-Thyristor Associations for a New Power Integrated Function: the IGTH 探索各种mos晶闸管的新型功率集成功能:IGTH
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194795
M. Breil, J. Sanchez, P. Austin, J. Laur, J. Jalade, J. Quoirin
{"title":"Exploring Various MOS-Thyristor Associations for a New Power Integrated Function: the IGTH","authors":"M. Breil, J. Sanchez, P. Austin, J. Laur, J. Jalade, J. Quoirin","doi":"10.1109/ESSDERC.2000.194795","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194795","url":null,"abstract":"In this paper, various MOS-thyristor associations are investigated in order to develop a new integrated power switch : the IGTH, which combines a thyristor mode in the on-state and IGBT turn-on switching characteristics, allowing the turn-on current waveform control. This function offers the advantages of a thyristor on-state whilst reducing ElectroMagnetic Interference (EMI) due to hard switching modes. The physical behavior of the various MOS-thyristor associations are analized using 2D numerical simulations. An optimized device has been fabricated and experimental switching waveforms are presented.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116823718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Red Vertical Cavity Surface Emitting Laser Technology 红色垂直腔面发射激光技术
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194722
J. Lambkin
{"title":"Red Vertical Cavity Surface Emitting Laser Technology","authors":"J. Lambkin","doi":"10.1109/ESSDERC.2000.194722","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194722","url":null,"abstract":"Vertical Cavity Surface Emitting Lasers (VCSELs) have over the last few years become a commercial reality. By far the most successful devices are those operating at 850 nm for use in high-speed data communication applications. However, considerable commercial opportunities also exist for VCSELs that can operate at the longer telecommunications wavelengths as well as opportunities at the shorter visible wavelengths of around 650 nm. VCSELs operating at both these wavelength bands have severe technological difficulties to over come before they match the performance and success of their near infra-red cousins. This paper will describe in particular the evolution of visible (red) VCSELs, indicating the technical issues that must still be resolved and the future prospects for these devices.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116557139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dependence of Channel Width and Length on MOSFET Matching for 0.18 um CMOS Technology 0.18 um CMOS技术中通道宽度和长度对MOSFET匹配的影响
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194845
R. Difrenza, P. Llinares, G. Ghibaudo, E. Robillart, E. Granger
{"title":"Dependence of Channel Width and Length on MOSFET Matching for 0.18 um CMOS Technology","authors":"R. Difrenza, P. Llinares, G. Ghibaudo, E. Robillart, E. Granger","doi":"10.1109/ESSDERC.2000.194845","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194845","url":null,"abstract":"Mismatch characterization has been performed on 0.18 μm CMOS technology for a wide range of dimensions for both N and P MOSFETs. It is the first time that a great number of dimensions has been tested : this allows to show the evolution of mismatch parameter AVt with both length and width. Matching degradation for short devices is related to the increase of effective channel doping level associated to the larger pocket influence. The effect of lateral isolation on the distribution of polysilicon grain size and orientation could explain mismatch decrease for narrow channel devices.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114874231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Extending KrF Lithography to 0.13 um sub-8F2 DRAM Technology: The Importance of Lithography-Centric Design 将KrF光刻扩展到0.13 um sub-8F2 DRAM技术:以光刻为中心设计的重要性
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194747
S. Bukofsky, A. Thomas, G. Kunkel, J. Preuninger
{"title":"Extending KrF Lithography to 0.13 um sub-8F2 DRAM Technology: The Importance of Lithography-Centric Design","authors":"S. Bukofsky, A. Thomas, G. Kunkel, J. Preuninger","doi":"10.1109/ESSDERC.2000.194747","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194747","url":null,"abstract":"Conventional optical lithography using a KrF excimer laser (λ =248 nm) is routinely used to manufacture DRAM technologies at ground rules as small as 0.15 μm. Due to the relative immaturity of ArF (λ =193 nm) lithography, it is desirable to continue to use KrF lithography for ground rules in the 0.13 μm regime. Simultaneously, continued DRAM chip scaling has led to investigation of open bit line architectures, whose theoretical minimum cell size is 4F, where F is the minimum feature dimension. This has die size advantages over the 8F minimum cell area of a conventional folded bit line cell. This cell architecture, combined with aggressive ground rule scaling, presents a unique challenge for optical lithography. In this paper, we discuss the evolution of sub-8F cell designs relative to lithographic difficulty, and present examples of design sorting for best lithographic performance.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128678367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modelling of Intrinsic Aluminum Diffusion for Future Power Devices 未来电力设备铝本征扩散的建模
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194743
O. Krause, P. Pichler, H. Ryssel
{"title":"Modelling of Intrinsic Aluminum Diffusion for Future Power Devices","authors":"O. Krause, P. Pichler, H. Ryssel","doi":"10.1109/ESSDERC.2000.194743","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194743","url":null,"abstract":"Aluminum as the fastest diffusing acceptor dopant in silicon is commonly used for the fabrication of power semiconductors with p n junctions depths ranging from microns to more than hundred micron. Although used since long, its diffusion behavior is not sufficiently characterized to support computer aided design of new devices. Since modern processes are rather based on low temperatures, the inert diffusion of aluminum was investigated in the temperature range from 850 to 1100 C. Combining nitridation and oxidation experiments, the fractional diffusivity via self interstitials was determined.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128863371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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