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Transport mechanisms of a polysilicon emitter bipolar transistor with 8 nm gate oxide between emitter and base 在发射极和基极之间具有8nm栅极氧化物的多晶硅发射极双极晶体管的输运机制
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194852
M.R. van den Berg, L. Nanver, C. D. de Boer, C. Visser, J. Slotboom
{"title":"Transport mechanisms of a polysilicon emitter bipolar transistor with 8 nm gate oxide between emitter and base","authors":"M.R. van den Berg, L. Nanver, C. D. de Boer, C. Visser, J. Slotboom","doi":"10.1109/ESSDERC.2000.194852","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194852","url":null,"abstract":"The current mechanisms through 8 nm thermal oxide have been studied by integrating the MOS capacitor at the emitter-base junction in a bipolar NPN structure. The separation of the electron and hole flow into a collector and base current, respectively, enhances the possibility of identifying the origin of currents in MOS structures in general. Here, the temperature dependence of the generated charge carriers in relation to the tunneling current for both bias polarities on the gate has been measured. It is demonstrated that the anode hole injection concept can be excluded as the dominant current mechanism.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127156159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integrated Transmission Lines on High-Resistivity Silicon: Coplanar Waveguides or Microstrips? 高电阻硅集成传输线:共面波导还是微带?
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194814
B. Rejaei, K. Ng, C. Floerkemeier, N. Pham, L. Nanver, J. Burghartz
{"title":"Integrated Transmission Lines on High-Resistivity Silicon: Coplanar Waveguides or Microstrips?","authors":"B. Rejaei, K. Ng, C. Floerkemeier, N. Pham, L. Nanver, J. Burghartz","doi":"10.1109/ESSDERC.2000.194814","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194814","url":null,"abstract":"We present an experimental study of the effect of the accumulation or inversion layer at the surface of a high-resistivity silicon substrate on the loss of transmission lines. It is shown that the relative contribution of the surface channel to the total loss becomes increasingly significant as the silicon resistivity decreases. The experiments demonstrate that the effect of the surface channel on the loss of an integrated microstrip is considerably lower than that of a comparable coplanar waveguide, favoring microstrips for integration on high-resistivity silicon substrates.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Ultra-Thin High Quality Oxynitride Formed by NH3 Nitridation and High Pressure O2 Re-oxidation NH3氮化与高压O2再氧化制备超薄高品质氮化氧
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194800
T. Luo, V. Watt, H. Al-Shareef, G.A. Brown, A. Karamcheti, M. Jackson, H. Huff, B. Evans, D. Kwong
{"title":"Ultra-Thin High Quality Oxynitride Formed by NH3 Nitridation and High Pressure O2 Re-oxidation","authors":"T. Luo, V. Watt, H. Al-Shareef, G.A. Brown, A. Karamcheti, M. Jackson, H. Huff, B. Evans, D. Kwong","doi":"10.1109/ESSDERC.2000.194800","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194800","url":null,"abstract":"In this paper, a novel technique to engineer the nitrogen profile in an ultra-thin silicon nitride-oxide gate stack is presented. It was found that the re-oxidation of silicon nitride, formed by NH3-nitridation, in a vertical high pressure (VHP) O2 furnace effectively moves the nitrogen-rich layer toward the top interface by growing pure oxide underneath. The impact of NH3 nitridation temperature and VHP O2 re-oxidation time on gate dielectric stack thickness was also investigated. Electrical measurements on NMOS transistors fabricated with this gate dielectric stack exhibit more than 10 times lower gate leakage currents, significantly enhanced drain current driveability, and comparable channel carrier mobility and hot carrier immunity, as compared to SiO2 of similar effective thickness grown by rapid thermal oxidation (RTO).","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132561632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of Second Impact Ionization Phenomena Between 0.18um N- and P-channel MOSFET's 0.18um N沟道和p沟道MOSFET二次冲击电离现象的比较
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194734
A. Bravaix, D. Goguenheim, N. Revil, E. Vincent
{"title":"Comparison of Second Impact Ionization Phenomena Between 0.18um N- and P-channel MOSFET's","authors":"A. Bravaix, D. Goguenheim, N. Revil, E. Vincent","doi":"10.1109/ESSDERC.2000.194734","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194734","url":null,"abstract":"The consequence of the second impact ionization phenomena (2II) with the back-bias VB differs significantly between Nand PMOSFET’s where electron or hole emissions are favored in the ionization processes. In PMOS a direct hole gate-current is now observed like the electronic one, as a function of the lateral field due to the first ionization event (II) which are both strongly reduced with VB during 2II effects. This behavior is opposite to the NMOS one where the II and 2II electronic gate-current is easily enhanced at lower field towards the NMOS gate by the conjonction of the thermionicand tunneling emissions. These results are explained by the localization of the emission point under the gate and by the hole energy loss which reduces the hole gate-current.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132651376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fabrication of GaN LEDs for Optical Communications 光通信用GaN发光二极管的制备
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194811
M. Akhter, P. Maaskant, J. Lambkin, L. Considine
{"title":"Fabrication of GaN LEDs for Optical Communications","authors":"M. Akhter, P. Maaskant, J. Lambkin, L. Considine","doi":"10.1109/ESSDERC.2000.194811","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194811","url":null,"abstract":"In this paper we report on the device fabrication and characterisation of InGaN/GaN multiple quantum well LEDs on sapphire substrates. Contact with the pGaN is made through a current spreading layer consisting of semi-transparent metal. IV curves and electroluminescence spectra have been measured. Devices that showed non-rectifying behaviour have been investigated and it is suggested that metal migration along defect tubes is the likely cause of these failures. It is recommended to use lower alloying temperatures for the p-contact metallisation in order to avoid this type of failure.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Frequency Noise in CdSe Thin-Film Transistors CdSe薄膜晶体管中的低频噪声
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194847
M. Deen, S. Rumyantsev, D. Landheer, D. Xu
{"title":"Low Frequency Noise in CdSe Thin-Film Transistors","authors":"M. Deen, S. Rumyantsev, D. Landheer, D. Xu","doi":"10.1109/ESSDERC.2000.194847","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194847","url":null,"abstract":"Low frequency noise in CdSe thin-film transistors (TFTs) has been studied, for the first time, over a wide range of gate and drain biases, temperatures and gate areas. The dependencies of the noise on the gate voltage and the gate length indicate that the 1/f noise originates from the bulk sources homogeneously distributed in the channel. The value of Hooge parameter α lies within the usual range for Si TFTs and amorphous Si. The absence of the illumination effect on the relative noise spectra of drain current fluctuations reveals that the nature of the 1/f noise in CdSe is probably different from that in Si and GaAs.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121237444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Using Ge pre-amorphisation and spike annealing for optimizing shallow junctions in deep-submicron CMOS 利用锗预非晶化和尖峰退火优化深亚微米CMOS的浅结
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194798
V. Meyssen, P. Stolk, J. van Zijl, J. van Berkum, W.G. van der Wijgert
{"title":"Using Ge pre-amorphisation and spike annealing for optimizing shallow junctions in deep-submicron CMOS","authors":"V. Meyssen, P. Stolk, J. van Zijl, J. van Berkum, W.G. van der Wijgert","doi":"10.1109/ESSDERC.2000.194798","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194798","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124766044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RF Distortion Characterisation of Sub-Micron CMOS 亚微米CMOS射频失真特性研究
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194815
L. Tiemeijer, R. Van Langevelde, O. Gaillard, R. Havens, P. Baltus, P. Woerlee, D. Klaassen
{"title":"RF Distortion Characterisation of Sub-Micron CMOS","authors":"L. Tiemeijer, R. Van Langevelde, O. Gaillard, R. Havens, P. Baltus, P. Woerlee, D. Klaassen","doi":"10.1109/ESSDERC.2000.194815","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194815","url":null,"abstract":"Distortion measurements up to 1 GHz ground tone for 3 different sub-micron CMOS technologies with minimum gatelengths down to 0.18 comply well with an accurate compact model. Using a new linearity figure of merit measurements are presented, which show that up to 1 GHz a high linearity at practical bias conditions is obtained because the distortion still predominantly originates from the nonlinear IV characteristics.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124977783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The Orientation Dependence of the Piezojunction Effect in Bipolar Transistors 双极晶体管中压电结效应的方向依赖性
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194803
J. Creemer, P. French
{"title":"The Orientation Dependence of the Piezojunction Effect in Bipolar Transistors","authors":"J. Creemer, P. French","doi":"10.1109/ESSDERC.2000.194803","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194803","url":null,"abstract":"Mechanical stress by packaging and processing can considerably change the saturation current of bipolar transistors. This effect was usually modelled through the stress-induced change in the intrinsic carrier concentration, which depends on the orientation of the stress. This change has now been calculated for silicon for different uniaxial stresses up to 200 MPa. It has been found to vary parabolically with stress, especially for the <100> directions. Measurements show a similar variation of the collector current. These measurements were done on both pnp and npn transistors, for different orientations of current and stress. They also show that the change in the minority mobility cannot be neglected for the stress range considered. It strongly depends on the minority type and the direction of its current through the base.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125181739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Optimisation of a TiSi2 SALICIDE Process in a 0.18 um CMOS Technology with Dual Selective Etch Process TISE2 采用双选择性蚀刻工艺的0.18 um CMOS工艺优化TiSi2 SALICIDE工艺
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194763
G. Pares, M. Basso, S. Rayr, M. Haond
{"title":"Optimisation of a TiSi2 SALICIDE Process in a 0.18 um CMOS Technology with Dual Selective Etch Process TISE2","authors":"G. Pares, M. Basso, S. Rayr, M. Haond","doi":"10.1109/ESSDERC.2000.194763","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194763","url":null,"abstract":"The use of TiSi2 Salicide for sub-quarter micron technologies is principally limited by the line width dependence effect. An other important limitation is the reactivity of Ti with respect to silicon oxide and silicon nitride which may lead to shorts between poly and active area commonly named bridging . This last effect makes, the selective etch process very critical, especially because the selectivity between TiN/Ti and TiSi2 is poor with a conventional NH4OH:H2O2:H2O (SC1) chemistry and results in a loss of a substantial part of the formed silicide thickness and hence in an increase of the line resistance. In this paper we propose an original solution consisting in a two step etch called TISE2 for TItanium Selective Etch. This process allows an important reduction of the TiSi2 thickness loss and hence, of the sheet resistance of the lines.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121878618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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