Optimisation of a TiSi2 SALICIDE Process in a 0.18 um CMOS Technology with Dual Selective Etch Process TISE2

G. Pares, M. Basso, S. Rayr, M. Haond
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Abstract

The use of TiSi2 Salicide for sub-quarter micron technologies is principally limited by the line width dependence effect. An other important limitation is the reactivity of Ti with respect to silicon oxide and silicon nitride which may lead to shorts between poly and active area commonly named bridging . This last effect makes, the selective etch process very critical, especially because the selectivity between TiN/Ti and TiSi2 is poor with a conventional NH4OH:H2O2:H2O (SC1) chemistry and results in a loss of a substantial part of the formed silicide thickness and hence in an increase of the line resistance. In this paper we propose an original solution consisting in a two step etch called TISE2 for TItanium Selective Etch. This process allows an important reduction of the TiSi2 thickness loss and hence, of the sheet resistance of the lines.
采用双选择性蚀刻工艺的0.18 um CMOS工艺优化TiSi2 SALICIDE工艺
在亚四分之一微米技术中使用TiSi2 Salicide主要受到线宽依赖效应的限制。另一个重要的限制是钛相对于氧化硅和氮化硅的反应性,这可能导致通常称为桥接的多晶硅和有源硅之间的短路。这最后一个影响使得选择性蚀刻过程非常关键,特别是因为TiN/Ti和TiSi2之间的选择性在传统的NH4OH:H2O2:H2O (SC1)化学反应中很差,导致形成的硅化物厚度的很大一部分损失,因此线电阻增加。在本文中,我们提出了一个原始的解决方案,包括在一个两步蚀刻称为TISE2钛选择性蚀刻。这一过程可以大大减少TiSi2厚度损失,从而减少线的片电阻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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