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Investigation of 3D Phenomena in the Triggering of gg-nMOS Electrostatic Discharge Protection Devices gg-nMOS静电放电保护装置触发的三维现象研究
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194829
M. Litzenberger, C. Furbock, D. Pogany, E. Gornik, K. Esmark, H. Gossner
{"title":"Investigation of 3D Phenomena in the Triggering of gg-nMOS Electrostatic Discharge Protection Devices","authors":"M. Litzenberger, C. Furbock, D. Pogany, E. Gornik, K. Esmark, H. Gossner","doi":"10.1109/ESSDERC.2000.194829","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194829","url":null,"abstract":"We study inhomogeneity in the triggering of the parasitic bipolar transistor during high current stress in the 0.35 μm process grounded-gate nMOS electrostatic discharge (ESD) protection devices by a laser interferometric technique. The current density and triggering width in partially and fully triggered devices are studied as a function of stress current. On the basis of experiments, 3D simulation and a simple model we explain the observed high current I-V characteristics.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115026205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Statistical Hot-Carrier Reliability Simulation using a Novel SPICE Parameter Evolution Model 基于SPICE参数演化模型的热载波可靠性统计仿真
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194853
S. Minehane, K. McCarthy, P. O'Sullivan, A. Mathewson
{"title":"Statistical Hot-Carrier Reliability Simulation using a Novel SPICE Parameter Evolution Model","authors":"S. Minehane, K. McCarthy, P. O'Sullivan, A. Mathewson","doi":"10.1109/ESSDERC.2000.194853","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194853","url":null,"abstract":"One of the key components in any circuit reliability simulation methodology is a strategy for predicting the hot-carrierinduced changes in device parameters during stress. In the context of SPICE MOSFET model parameter shifts, the parameter extraction methodology utilised contributes to the “ease” in which parameter degradation trends can be modelled. This paper will demonstrate that direct parameter extraction techniques produce more monotonic parameter degradation trends than conventional optimisation techniques. In addition, a novel approach for the modelling of the evolution of directly-extracted parameters during hot-carrier stress is presented. Finally, a statistical validation, comparing measured and simulated degraded ring oscillator data, is presented.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115147699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MOS Memory Using Silicon Nanocrystals Formed by Very-Low Energy Ion Implantation 极低能量离子注入形成的硅纳米晶MOS存储器
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194818
E. Kapetanakis, P. Normand, D. Tsoukalas, G. Kamoulakos, D. Kouvatsos, J. Stoemenos, S. Zhang, J. A. Van den Berg, D. Armour
{"title":"MOS Memory Using Silicon Nanocrystals Formed by Very-Low Energy Ion Implantation","authors":"E. Kapetanakis, P. Normand, D. Tsoukalas, G. Kamoulakos, D. Kouvatsos, J. Stoemenos, S. Zhang, J. A. Van den Berg, D. Armour","doi":"10.1109/ESSDERC.2000.194818","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194818","url":null,"abstract":"Metal Oxide Semiconductor Field Effect Transistor (MOSFET) memory devices using silicon nanocrystals as charge storage elements have been fabricated. The nanocrystals are obtained by Si ion implantation at very low energy (1keV) into a thin thermal oxide (8 nm) and subsequent annealing. The memory characteristics of the devices under static and dynamic operation are reported. These devices exhibit fast write/erase characteristics at low voltage operation. The presence of interface states and defects that originate from the nanocrystal formation process is also found to have a strong effect on the device transfer characteristics.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115618244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High hole mobilities in fullly-strained Si/Si(1-x)Ge(x) (0.3 < x < 0.4) layers and their significance for SiGe pMOSFET performance 全应变Si/Si(1-x)Ge(x) (0.3 &lt)中高空穴迁移率;x & lt;0.4)层及其对SiGe pMOSFET性能的意义
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194746
R. Lander, Y. Ponomarev, W.B. de Boer
{"title":"High hole mobilities in fullly-strained Si/Si(1-x)Ge(x) (0.3 &lt; x &lt; 0.4) layers and their significance for SiGe pMOSFET performance","authors":"R. Lander, Y. Ponomarev, W.B. de Boer","doi":"10.1109/ESSDERC.2000.194746","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194746","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123211705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
IC-Compatible Two-level Bulk Micromachining for RF Silicon Technology 射频硅技术的ic兼容两级体微加工
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194750
N. Pham, P. Sarro, K. Ng, J. Burghartz
{"title":"IC-Compatible Two-level Bulk Micromachining for RF Silicon Technology","authors":"N. Pham, P. Sarro, K. Ng, J. Burghartz","doi":"10.1109/ESSDERC.2000.194750","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194750","url":null,"abstract":"This paper presents a novel two-level silicon bulk micromachining for integration of RF (radio frequency) devices. The RF devices are fabricated at the frontside of Si (100) wafers using conventional IC technology. A post-processing module is applied from the wafer backside. This module provides a blanket ground plane at an optimum position beneath the wafer surface, a front-side contact from the wafer surface to that ground plane and trenches to suppress cross talk through the conductive silicon. Moreover, due to the front-side RF ground contact, compatibility to conventional packaging is maintained. The feasibility of the new postprocess module is demonstrated through the fabrication of microstrip transmission lines and conductor-backed spiral inductors.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122661790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Copper Drifts in Porous Methylsilsesquiazane Low-k Dielectric Films 低钾甲基硅氧烷多孔介质膜中铜的漂移
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194751
T. Kikkawa, S. Mukaigawa, T. Oda, T. Aoki, Y. Shimizu
{"title":"Copper Drifts in Porous Methylsilsesquiazane Low-k Dielectric Films","authors":"T. Kikkawa, S. Mukaigawa, T. Oda, T. Aoki, Y. Shimizu","doi":"10.1109/ESSDERC.2000.194751","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194751","url":null,"abstract":"Copper drift rates were measured in porous low-dielectric-constant methylsilsesquioxane films derived from methylsilsesquiazane (MSZ) precursor. It is found that the porous MSZ film shows a lower dielectric constant (k=1.8) and a slower drift rate than that of CVD-SiO 2 .","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Capacitance Modelling of LDMOS Transistors LDMOS晶体管的电容建模
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194855
E. Griffith, S. C. Kelly, J. A. Power, D. Bain, S. Whiston, P. Elbert, M. O’Neill
{"title":"Capacitance Modelling of LDMOS Transistors","authors":"E. Griffith, S. C. Kelly, J. A. Power, D. Bain, S. Whiston, P. Elbert, M. O’Neill","doi":"10.1109/ESSDERC.2000.194855","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194855","url":null,"abstract":"High Voltage integrated circuits (HVIC’s) are emerging as viable alternatives to discrete circuits in a wide variety of applications. A commonly used High Voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). Modelling the LDMOS transistor is complicated by the existence of the lightly doped drain and by the extension of the gate oxide and polysilicon beyond the channel region into the drain region. This lightly doped drain has a large effect on the feedback capacitance of the device. This paper will discuss the modelling of the capacitances associated with a LDMOS transistor integrated into a conventional 0.6μm CMOS technology.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129809527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Comparison of PNP and NPN SiGe Heterojunction Bipolar Transistors Fabricated by Ge(+)-implantation Ge(+)注入制备PNP和NPN SiGe异质结双极晶体管的比较
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194761
M. Mitchell, P. Ashburn, H. Graoui, P. Hemment, A. Lamb, S. Hall, S. Nigrin
{"title":"A Comparison of PNP and NPN SiGe Heterojunction Bipolar Transistors Fabricated by Ge(+)-implantation","authors":"M. Mitchell, P. Ashburn, H. Graoui, P. Hemment, A. Lamb, S. Hall, S. Nigrin","doi":"10.1109/ESSDERC.2000.194761","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194761","url":null,"abstract":"A study is made of npn and pnp SiGe heterojunction bipolar transistors produced using Ge+-implantation. The Ge+ is implanted into a complementary bipolar process after active area formation. Increased collector currents are observed in both npn and pnp transistors due to the presence of the Ge. The implanted Ge+ has opposing effects on the emitter dopant diffusion increasing the arsenic diffusion coefficient in the npn devices and retarding the boron diffusion coefficient in the pnp devices.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130151499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime 低电压下传统和非对称沟道mosfet栅极氧化物可靠性的漏极偏置依赖性
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194730
K. Anil, S. Mahapatra, I. Eisele, V. Rao, J. Vasi
{"title":"Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime","authors":"K. Anil, S. Mahapatra, I. Eisele, V. Rao, J. Vasi","doi":"10.1109/ESSDERC.2000.194730","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194730","url":null,"abstract":"Drain bias dependence of gate oxide reliability is investigated on conventional (CON) and Lateral Asymmetric Channel (LAC) MOSFETs for low drain voltages that correspond to the real operating voltages for deep-sub-micron devices. For short channel devices, the oxide reliability improves drastically as drain bias increases. Device simulations showed that the vertical field distribution in the oxide is asymmetric for non-zero drain biases and this results in an asymmetric gate current distribution with the peak at the source end. By introducing an intentionally graded doping profile along the channel (LAC), the asymmetry in the vertical filed distribution can be enhanced with consequent improvement in gate oxide reliability.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127846574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improved Output Conductance for Low-Voltage Microwave LDMOS Transistors 改进的低压微波LDMOS晶体管输出电导
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194816
L. Vestling, R. Valtonen, U. Heinle, J. Ankarcrona, J. Olsson
{"title":"Improved Output Conductance for Low-Voltage Microwave LDMOS Transistors","authors":"L. Vestling, R. Valtonen, U. Heinle, J. Ankarcrona, J. Olsson","doi":"10.1109/ESSDERC.2000.194816","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194816","url":null,"abstract":"A low voltage LDMOS transistor has been investigated in terms of output conductance and its affect on and . By process modifications the output conductance has been reduced resulting in =7.8 GHz and =15.6 GHz for a device with =0.75 . The ratio was increased with 32 % and the breakdown voltage increased from 11 V to 16 V.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116741500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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