Capacitance Modelling of LDMOS Transistors

Abstract

High Voltage integrated circuits (HVIC’s) are emerging as viable alternatives to discrete circuits in a wide variety of applications. A commonly used High Voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). Modelling the LDMOS transistor is complicated by the existence of the lightly doped drain and by the extension of the gate oxide and polysilicon beyond the channel region into the drain region. This lightly doped drain has a large effect on the feedback capacitance of the device. This paper will discuss the modelling of the capacitances associated with a LDMOS transistor integrated into a conventional 0.6μm CMOS technology.