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The Impact of SiGe BiCMOS Technology on Microwave Circuits and Systems SiGe BiCMOS技术对微波电路和系统的影响
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194715
M. Soyuer
{"title":"The Impact of SiGe BiCMOS Technology on Microwave Circuits and Systems","authors":"M. Soyuer","doi":"10.1109/ESSDERC.2000.194715","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194715","url":null,"abstract":"This paper focuses on low power and high integration capabilities of SiGe BiCMOS technology and describes the performance improvements which can be obtained by its utilization in mixed-signal microwave circuits and systems. By way of examples, the article highlights the fact that the combination of high-bandwidth, high-gain and low-noise SiGe HBT s with dense CMOS functionality in a SiGe BiCMOS technology enables implementation of powerful single-chip transceiver architectures for multi-GHz and multi-Gb/s communication applications.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133764546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A comparison between semi-classical and quantum-mechanical escape-times for gate current calculations 门电流计算的半经典和量子力学逃逸时间的比较
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194784
A. Serra, A. Abramo, P. Palestri, L. Selmi, F. Widdershoven
{"title":"A comparison between semi-classical and quantum-mechanical escape-times for gate current calculations","authors":"A. Serra, A. Abramo, P. Palestri, L. Selmi, F. Widdershoven","doi":"10.1109/ESSDERC.2000.194784","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194784","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132719193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance 最佳CMOS逻辑电路性能的氧化物厚度缩放限制
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194774
K. Bowman, Lihui Wang, Xinghai Tang, J. Meindl
{"title":"Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance","authors":"K. Bowman, Lihui Wang, Xinghai Tang, J. Meindl","doi":"10.1109/ESSDERC.2000.194774","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194774","url":null,"abstract":"The gate tunneling power is demonstrated through analysis as well as physical insight to be negligible (<5%) in comparison to the source-to-drain leakage power at the oxide thickness required for optimum CMOS logic circuit performance. The scaling limit of tOX is projected as 2.2, 1.9 and 1.4 nm for the 180, 150 and 100 nm technology generations, respectively.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125802309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Observation of a New Hole Gate Current Component in p(+)-poly Gate p-channel MOSFET's p(+)-多栅极p沟道MOSFET中新型孔栅电流分量的观察
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194733
F. Driussi, D. Esseni, L. Selmi, F. Piazza
{"title":"Observation of a New Hole Gate Current Component in p(+)-poly Gate p-channel MOSFET's","authors":"F. Driussi, D. Esseni, L. Selmi, F. Piazza","doi":"10.1109/ESSDERC.2000.194733","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194733","url":null,"abstract":"This paper reports experimental evidence of a new, substrate-enhanced component of the gate current of -poly gate pMOS transistors. The phenomenon is characterized as a function of drain, gate and substrate bias on devices featuring three different drain engineering options. The new current component is ascribed to an impact ionization feedback mechanism similar to that responsible of CHISEL in nMOSFETs.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129924018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Complete re-estimation of the gate leakage current limit for sub-0.12um technologies (EOT= 1.8-2.8nm) 0.12um以下技术栅极泄漏电流极限的完全重新估计(EOT= 1.8-2.8nm)
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194775
M. Bidaud, F. Arnaud, J. Autran, K. Barla
{"title":"Complete re-estimation of the gate leakage current limit for sub-0.12um technologies (EOT= 1.8-2.8nm)","authors":"M. Bidaud, F. Arnaud, J. Autran, K. Barla","doi":"10.1109/ESSDERC.2000.194775","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194775","url":null,"abstract":"To control short channel effects and improve device performances, gate oxides as thin as 2.0nm are foreseen for sub0.12μm technologies. As a consequence, the gate tunneling current is found to increase tremendously so that it can disturb the device operation. In this paper, we clearly show that conventional SiO2 gate oxides reach their fundamental leakage limit for effective thickness below 2.3nm. This limit is established regarding both static and dynamic operations.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122971738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A GaAs Device Isolation Technique by Liquid Phase Chemical-Enhanced Oxidation 液相化学强化氧化的砷化镓器件分离技术
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194807
H. Wang, D. Chou, J. Wu, Y.H. Wang, M. Houng
{"title":"A GaAs Device Isolation Technique by Liquid Phase Chemical-Enhanced Oxidation","authors":"H. Wang, D. Chou, J. Wu, Y.H. Wang, M. Houng","doi":"10.1109/ESSDERC.2000.194807","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194807","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"628 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115961397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
1/f Noise Modeling in a-Si TFTs by BSIM Software 1/f基于BSIM软件的a-Si TFTs噪声建模
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194737
J. Rhayem, D. Rigaud, T. Contaret, M. Valenza, N. Szydlo, H. Lebrun
{"title":"1/f Noise Modeling in a-Si TFTs by BSIM Software","authors":"J. Rhayem, D. Rigaud, T. Contaret, M. Valenza, N. Szydlo, H. Lebrun","doi":"10.1109/ESSDERC.2000.194737","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194737","url":null,"abstract":"1/f noise has been studied in amorphous silicon inverted staggered thin film transistors over different gate geometries. It is shown that the origin of this noise changes when the gate area is scaled down. For large gate geometries mobility fluctuations (Hooge model) prevail whereas for small gate dimensions correlated number-mobility fluctuations (∆N-∆μ model) are involved. In any case, we have used BSIM to obtain 1/f noise modeling. It is pointed out some terms in order to obtain simulation accuracy. Good agreement is observed showing BSIM possibilities to model excess noise in thin film devices.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127206117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Technology Requirements for Next Decade Flash Memories 下一个十年闪存的技术要求
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194721
K. Yoshikawa
{"title":"Technology Requirements for Next Decade Flash Memories","authors":"K. Yoshikawa","doi":"10.1109/ESSDERC.2000.194721","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194721","url":null,"abstract":"Technology challenges for current flash memories are given for aiming technology survival beyond the 0.13 m. Basic concepts of current flash devices are critically reviewed to clarify technology challenges. Various approaches and research items will be discussed from broad viewpoints, such as reliability, dielectric/device physics, process integration, ---. Future promising cell structure will be also addressed.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128194405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparison of two High-Frequency Noise Characterization Methods for SiGe HBTs SiGe HBTs两种高频噪声表征方法的比较
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194792
B. Malm, J. Grahn, M. Ostling, J. Stenarson
{"title":"Comparison of two High-Frequency Noise Characterization Methods for SiGe HBTs","authors":"B. Malm, J. Grahn, M. Ostling, J. Stenarson","doi":"10.1109/ESSDERC.2000.194792","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194792","url":null,"abstract":"The high-frequency (HF) noise properties of devices fabricated in a 60 GHz fT SiGe HBT process have been investigated, using a recently developed approach based on direct y-parameter measurements. The results were compared to conventional noise figure measurements and good agreement was observed between the two methods. The accuracy of the noise parameters was improved and the measurement time was greatly reduced by using direct y-parameter measurements. Furthermore, the method enabled an analysis of the relative contributions of the different noise sources as a function of bias and frequency.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121924337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact on Low-Frequency Noise Properties from Lateral Design of Differentially Grown SiGe HBTs 横向设计对差分生长SiGe HBTs低频噪声特性的影响
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194840
M. Sandén, B. Malm, J. Grahn, M. Ostling
{"title":"Impact on Low-Frequency Noise Properties from Lateral Design of Differentially Grown SiGe HBTs","authors":"M. Sandén, B. Malm, J. Grahn, M. Ostling","doi":"10.1109/ESSDERC.2000.194840","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194840","url":null,"abstract":"SiGe heterojunction bipolar transistors (HBTs) are suitable for wireless applications due to their high speed, low high-frequency noise and low power dissipation. For some applications, such as voltage-controlled oscillators (VCO’s), the device must also exhibit low 1/ noise which will act to suppress undesired phase noise. In this work, SiGe HBTs based on chemical vapour deposition (CVD) epitaxy have been studied. The SiGe epitaxial film was grown differentially with a monocrystalline phase on top of the silicon collector, and a polycrystalline phase on top of the LOCOS. Figure 1 shows a cross-sectional TEM picture of the HBT investigated in this work. The interface between the polycrystalline and epitaxial Si/SiGe stack ...............","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117181596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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