Complete re-estimation of the gate leakage current limit for sub-0.12um technologies (EOT= 1.8-2.8nm)

Abstract

To control short channel effects and improve device performances, gate oxides as thin as 2.0nm are foreseen for sub0.12μm technologies. As a consequence, the gate tunneling current is found to increase tremendously so that it can disturb the device operation. In this paper, we clearly show that conventional SiO2 gate oxides reach their fundamental leakage limit for effective thickness below 2.3nm. This limit is established regarding both static and dynamic operations.