Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance

Abstract

The gate tunneling power is demonstrated through analysis as well as physical insight to be negligible (<5%) in comparison to the source-to-drain leakage power at the oxide thickness required for optimum CMOS logic circuit performance. The scaling limit of tOX is projected as 2.2, 1.9 and 1.4 nm for the 180, 150 and 100 nm technology generations, respectively.