{"title":"最佳CMOS逻辑电路性能的氧化物厚度缩放限制","authors":"K. Bowman, Lihui Wang, Xinghai Tang, J. Meindl","doi":"10.1109/ESSDERC.2000.194774","DOIUrl":null,"url":null,"abstract":"The gate tunneling power is demonstrated through analysis as well as physical insight to be negligible (<5%) in comparison to the source-to-drain leakage power at the oxide thickness required for optimum CMOS logic circuit performance. The scaling limit of tOX is projected as 2.2, 1.9 and 1.4 nm for the 180, 150 and 100 nm technology generations, respectively.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance\",\"authors\":\"K. Bowman, Lihui Wang, Xinghai Tang, J. Meindl\",\"doi\":\"10.1109/ESSDERC.2000.194774\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The gate tunneling power is demonstrated through analysis as well as physical insight to be negligible (<5%) in comparison to the source-to-drain leakage power at the oxide thickness required for optimum CMOS logic circuit performance. The scaling limit of tOX is projected as 2.2, 1.9 and 1.4 nm for the 180, 150 and 100 nm technology generations, respectively.\",\"PeriodicalId\":354721,\"journal\":{\"name\":\"30th European Solid-State Device Research Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"30th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2000.194774\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"30th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2000.194774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance
The gate tunneling power is demonstrated through analysis as well as physical insight to be negligible (<5%) in comparison to the source-to-drain leakage power at the oxide thickness required for optimum CMOS logic circuit performance. The scaling limit of tOX is projected as 2.2, 1.9 and 1.4 nm for the 180, 150 and 100 nm technology generations, respectively.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
