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Dynamics of Fast-Erasing Bits in Flash Memories 快闪记忆体中快速擦除位的动态
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194771
P. Pellati, A. Chimenton, P. Olivo, A. Modelli
{"title":"Dynamics of Fast-Erasing Bits in Flash Memories","authors":"P. Pellati, A. Chimenton, P. Olivo, A. Modelli","doi":"10.1109/ESSDERC.2000.194771","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194771","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132052613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Inverse Modelling of Trapped Charge in Hot-Carrier Stressed nMOSFET 热载流子应力nMOSFET中捕获电荷的反演模型
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194791
R. Duane, A. Concannon, D. McCarthy, A. Mathewson
{"title":"Inverse Modelling of Trapped Charge in Hot-Carrier Stressed nMOSFET","authors":"R. Duane, A. Concannon, D. McCarthy, A. Mathewson","doi":"10.1109/ESSDERC.2000.194791","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194791","url":null,"abstract":"A new inverse modelling technique for extracting the spatial distribution of localised interface states after hot-carrier stress is presented. This technique shows for the first time quantitative agreement between measured and simulated currents in the subthreshold and weak inversion regions of operation during stress for the full range of drain, gate and bulk biases.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126900732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Investigation of the suitability of spike anneal for advanced CMOS technology 尖峰退火对先进CMOS技术的适用性研究
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194797
D. Lenoble, E. Josse, A. Grouillet, F. Arnaud, C. Julien, T. Skotnicki, M. Haond
{"title":"Investigation of the suitability of spike anneal for advanced CMOS technology","authors":"D. Lenoble, E. Josse, A. Grouillet, F. Arnaud, C. Julien, T. Skotnicki, M. Haond","doi":"10.1109/ESSDERC.2000.194797","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194797","url":null,"abstract":"The use of the spike anneal is an efficient process to reduce the diffusion length during the dopant activation step. We demonstrate subsequently that the spike anneal reduces the Short Channel Effects. We point out the fact that the global architecture of MOSFET needs to be optimized to take full advantage of the spike anneal without degrading poly-gate depletion and oxide reliability.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"75 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123157677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel DRAM Cell Transistor using Self Aligned Local Field Implantation (SALFI) for Enhanced Data Retention Time 采用自对准局部场植入(SALFI)的新型DRAM单元晶体管可提高数据保留时间
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194770
Jae-kyu Lee, Sang-Hyeon Lee, D. Ha, Kinam Kim
{"title":"Novel DRAM Cell Transistor using Self Aligned Local Field Implantation (SALFI) for Enhanced Data Retention Time","authors":"Jae-kyu Lee, Sang-Hyeon Lee, D. Ha, Kinam Kim","doi":"10.1109/ESSDERC.2000.194770","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194770","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121490556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Degradation of Si MOSFET Gate Oxides by Ion Implantation 离子注入降解硅MOSFET栅极氧化物
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194731
Y. Ponomarev, P. Stolk, C. Dachs, P. Woerlee
{"title":"Degradation of Si MOSFET Gate Oxides by Ion Implantation","authors":"Y. Ponomarev, P. Stolk, C. Dachs, P. Woerlee","doi":"10.1109/ESSDERC.2000.194731","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194731","url":null,"abstract":"We have characterised the effects of ion implantation in advanced MOSFETs, and have shown that severe gate oxide degradations can be induced by ion implantations used routinely in front-end processing of MOS transistors. The mechanisms of oxide degradation are revealed to be connected to the nuclear energy transfer to the O atoms in the oxide during implantation. Si and O ion mixing can result in significant increase of the effective oxide thickness which also result in intrinsic device performance degradation.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116498853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Test Structure for Sub-micron CMOS Leakage Characterisation and Modelling 一种新型的亚微米CMOS泄漏表征与建模测试结构
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194822
Z. Ning, S. Hoste, W. Vanderbauwhede, R. Gillon, M. Tack, P. Raes
{"title":"A Novel Test Structure for Sub-micron CMOS Leakage Characterisation and Modelling","authors":"Z. Ning, S. Hoste, W. Vanderbauwhede, R. Gillon, M. Tack, P. Raes","doi":"10.1109/ESSDERC.2000.194822","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194822","url":null,"abstract":"This paper presents a novel test structure for the characterisation and modelling of CMOS leakage current, with which all leakage components can be directly extracted automatically and input/output influence is cancelled. The test structure can also be used for measurement of Intrinsic Iddq for defect detection.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121269624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Proliferation of Silicon Germanium 硅锗的扩散
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194723
A. Schuppen, M. Tortschanoff, J. Berntgen, P. Maier, D. Zerrweck, H. von der Ropp, J. Tolonics, K. Burger
{"title":"The Proliferation of Silicon Germanium","authors":"A. Schuppen, M. Tortschanoff, J. Berntgen, P. Maier, D. Zerrweck, H. von der Ropp, J. Tolonics, K. Burger","doi":"10.1109/ESSDERC.2000.194723","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194723","url":null,"abstract":"SiGe has already penetrated into the III/V market by rf IC ́s in the 0.9-2.4 GHz range. SiGe technologies have a high reliability, operates also at low voltages and nevertheless it reveals 72% PAE @ GSM frequency, 60% PAE for a 3W DCS power HBT and 50% PAE for CDMA at 1.9GHz. Combined with flip chip technology TEMIC ́s SiGe1 process is well suited for rf power systems up to 6 GHz. For higher frequencies and due to performance pressure of pure Si from the bottom of the frequency scale and III/V devices from the top, the next generation: SiGe2 proliferates into III/V area in the 720 GHz range. SiGe2 technology includes three types of transistors on the same wafer, having 25, 40 and 70 GHz transit frequencies with 7, 4 and 2.5V BVCE0 corresponding breakdown voltages.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132528306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On the InGaP/In(x)Ga(1-x)As Pseudomorphic High Electron-Mobility Transistor s with High-Temperature Reliabilities 具有高温可靠性的InGaP/In(x)Ga(1-x)伪晶高电子迁移率晶体管
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194806
W. Liu, W.L. Chang, W. Lour, K. Yu, K.W. Lin, K. Lin, C. Yen
{"title":"On the InGaP/In(x)Ga(1-x)As Pseudomorphic High Electron-Mobility Transistor s with High-Temperature Reliabilities","authors":"W. Liu, W.L. Chang, W. Lour, K. Yu, K.W. Lin, K. Lin, C. Yen","doi":"10.1109/ESSDERC.2000.194806","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194806","url":null,"abstract":"We reported the high-temperature reliability characteristics of a novel InGaP/InxGa1-xAs pseudomorphic transistor with an inverted delta-doped channel in this work. Due to the presented wide-gap InGaP Schottky layer and the “V-shaped” InxGa1xAs channel structure, the degradation of device performance with increasing the temperature is not so significant. Experimentally, for a 1×100 μm device, the gate-drain voltages at a gate leakage current of 260 μA/mm and the maximum transconductances gm,max are 30 (22.2) V and 201 (169) mS/mm at the temperature of 300 K (450 K), respectively. Meanwhile, the broad and flat drain current operation regimes for high gm, fT, and fmax are obtained.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132006116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Present Understanding of Gate Oxide Wearout 目前对栅氧化磨损的认识
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194717
E. Rosenbaum, Jie Wu
{"title":"Present Understanding of Gate Oxide Wearout","authors":"E. Rosenbaum, Jie Wu","doi":"10.1109/ESSDERC.2000.194717","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194717","url":null,"abstract":"Generation of neutral electron traps in the gate oxide leads to degradation in the form of stress-induced leakage current and eventually results in breakdown. We review proposed mechanisms for oxide trap generation and show that the anode hole injection model most likely describes the correct mechanism. Stress-induced leakage is shown to be the result of inelastic trapassisted tunneling of electrons that originate in the cathode conduction band. A framework for modeling time-to-breakdown is presented.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134398740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Electron injection in MOSFETs with a self-consistent Si and SiO2 BTE solution based on spherical-harmonics expansion 基于球次谐波展开的自相容Si和SiO2 BTE溶液在mosfet中的电子注入
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194850
M. Marsella, S. Reggiani, A. Gnudi, M. Rudan
{"title":"Electron injection in MOSFETs with a self-consistent Si and SiO2 BTE solution based on spherical-harmonics expansion","authors":"M. Marsella, S. Reggiani, A. Gnudi, M. Rudan","doi":"10.1109/ESSDERC.2000.194850","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194850","url":null,"abstract":"The solution method for the Boltzmann Transport Equation (BTE) based on the spherical-harmonics expansion (SHE) has been applied to the transport problem in a Si-SiO2 structure. A new model has been introduced to calculate the microscopic fluxes at the interface between the two materials, based on the thermionic theory. Results of a 2D MOSFET simulation are shown to validate the model.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114429318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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