D. Lenoble, E. Josse, A. Grouillet, F. Arnaud, C. Julien, T. Skotnicki, M. Haond
{"title":"尖峰退火对先进CMOS技术的适用性研究","authors":"D. Lenoble, E. Josse, A. Grouillet, F. Arnaud, C. Julien, T. Skotnicki, M. Haond","doi":"10.1109/ESSDERC.2000.194797","DOIUrl":null,"url":null,"abstract":"The use of the spike anneal is an efficient process to reduce the diffusion length during the dopant activation step. We demonstrate subsequently that the spike anneal reduces the Short Channel Effects. We point out the fact that the global architecture of MOSFET needs to be optimized to take full advantage of the spike anneal without degrading poly-gate depletion and oxide reliability.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"75 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Investigation of the suitability of spike anneal for advanced CMOS technology\",\"authors\":\"D. Lenoble, E. Josse, A. Grouillet, F. Arnaud, C. Julien, T. Skotnicki, M. Haond\",\"doi\":\"10.1109/ESSDERC.2000.194797\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The use of the spike anneal is an efficient process to reduce the diffusion length during the dopant activation step. We demonstrate subsequently that the spike anneal reduces the Short Channel Effects. We point out the fact that the global architecture of MOSFET needs to be optimized to take full advantage of the spike anneal without degrading poly-gate depletion and oxide reliability.\",\"PeriodicalId\":354721,\"journal\":{\"name\":\"30th European Solid-State Device Research Conference\",\"volume\":\"75 5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"30th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2000.194797\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"30th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2000.194797","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Investigation of the suitability of spike anneal for advanced CMOS technology
The use of the spike anneal is an efficient process to reduce the diffusion length during the dopant activation step. We demonstrate subsequently that the spike anneal reduces the Short Channel Effects. We point out the fact that the global architecture of MOSFET needs to be optimized to take full advantage of the spike anneal without degrading poly-gate depletion and oxide reliability.