一种新型的亚微米CMOS泄漏表征与建模测试结构

30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI:10.1109/ESSDERC.2000.194822

Z. Ning, S. Hoste, W. Vanderbauwhede, R. Gillon, M. Tack, P. Raes

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引用次数: 0

摘要

本文提出了一种新型的CMOS泄漏电流表征和建模测试结构，该结构可以直接自动提取所有泄漏分量，并消除输入/输出影响。测试结构也可用于测量缺陷检测的固有Iddq。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Novel Test Structure for Sub-micron CMOS Leakage Characterisation and Modelling

This paper presents a novel test structure for the characterisation and modelling of CMOS leakage current, with which all leakage components can be directly extracted automatically and input/output influence is cancelled. The test structure can also be used for measurement of Intrinsic Iddq for defect detection.

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30th European Solid-State Device Research Conference

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