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Evaluation of Germanium JFET for low temperature operation 低温运行锗JFET的评价
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194808
N. Das, C. Monroy, M. Jhabvala, P. Shu
{"title":"Evaluation of Germanium JFET for low temperature operation","authors":"N. Das, C. Monroy, M. Jhabvala, P. Shu","doi":"10.1109/ESSDERC.2000.194808","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194808","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115390230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Area-Efficient ESD Protection Design without Additional Process Cost in 0.18 um Salicided CMOS Technology 0.18 um盐化CMOS技术无额外工艺成本的面积高效ESD保护设计
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194828
H. Kawazoe, E. Aoki, K. Fujii
{"title":"Area-Efficient ESD Protection Design without Additional Process Cost in 0.18 um Salicided CMOS Technology","authors":"H. Kawazoe, E. Aoki, K. Fujii","doi":"10.1109/ESSDERC.2000.194828","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194828","url":null,"abstract":"For the electrostatic discharge (ESD) protection design in deep-submicron CMOS technologies, it is desirable to develop ESD protection devices which can be fabricated without additional photo-masks and processes. And it is required to minimize the layout area of ESD protection circuits. In this work, we propose a new lateral silicon controlled rectifier (SCR) device as an ESD protection element, and propose area-efficient ESD protection circuits. The protection circuits can be made without any additional process in advanced salicided","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123641817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On a Novel Technique for the Electrical Characterization of Polycrystalline Silicon 多晶硅电学表征新技术的研究
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194804
A. Ionescu, J. Tringe, A. Chovet, J. Plummer
{"title":"On a Novel Technique for the Electrical Characterization of Polycrystalline Silicon","authors":"A. Ionescu, J. Tringe, A. Chovet, J. Plummer","doi":"10.1109/ESSDERC.2000.194804","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194804","url":null,"abstract":"The aim of this work is to evaluate the ability of a SOI pseudo-MOS-like technique to be tailored for polycrystalline silicon, in order to perform in situ bare material electrical characterization. The proposed technique and associated simple MOS-like models are validated on advanced, very narrow (down to 0.1μm width, i.e. less than grain size), fourcontact device geometries, for which few series-connected grains can be assumed. For the first time measurements of 1/f noise in pseudo-MOS operation are presented.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124626538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection 寄生基板电流注入时全芯片电位分布的测量和三维模拟
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194849
M. Schenkel, P. Pfaffli, S. Mettler, W. Reiner, W.D. Aemmer
{"title":"Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection","authors":"M. Schenkel, P. Pfaffli, S. Mettler, W. Reiner, W.D. Aemmer","doi":"10.1109/ESSDERC.2000.194849","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194849","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125631726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Abnormal Gate Oxide Failure due to Stress enhanced Polycrystalline Silicon Diffusion 应力增强多晶硅扩散引起的栅氧化异常失效
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194729
Yongseok Ahn, D. Ha, G. Koh, Taeyoung Chung, Kinam Kim
{"title":"Abnormal Gate Oxide Failure due to Stress enhanced Polycrystalline Silicon Diffusion","authors":"Yongseok Ahn, D. Ha, G. Koh, Taeyoung Chung, Kinam Kim","doi":"10.1109/ESSDERC.2000.194729","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194729","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116014388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single Trap Profiling by Charge Pumping 电荷泵送的单阱剖面
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194779
S. Okhonin, V. Meyer, A. Ils, P. Fazan, L. Risch, F. Hoffman
{"title":"Single Trap Profiling by Charge Pumping","authors":"S. Okhonin, V. Meyer, A. Ils, P. Fazan, L. Risch, F. Hoffman","doi":"10.1109/ESSDERC.2000.194779","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194779","url":null,"abstract":"We demonstrate that the CP characteristic of a single trap can be measured in relatively large MOSFETs or even in arrays of MOSFETs with common gates, common sources and separated drain contacts where the total quantity of interface traps can be as high as several thousands. The influence of CP parameters is also demonstrated. The possibility to use these results to study the influence of single trap on the GIDL is discussed.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121376707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Emitter Scaling of Single-Polysilicon SiGe:C HBTs with Highly Doped Base Layers 高掺杂基层单多晶硅SiGe:C HBTs的发射极缩放
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194839
D. Knoll, B. Heinemann, K. Ehwald, G. Fischer
{"title":"Emitter Scaling of Single-Polysilicon SiGe:C HBTs with Highly Doped Base Layers","authors":"D. Knoll, B. Heinemann, K. Ehwald, G. Fischer","doi":"10.1109/ESSDERC.2000.194839","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194839","url":null,"abstract":"We demonstrate that single-polysilicon SiGe:C heterojunction bipolar transistors with a very thin, highly doped SiGe layer can be scaled in the emitter width to 0.4 μm and in the emitter overlap to 0.2 μm without any indications of B outdiffusion from the SiGe:C base. Thus, transistors can be fabricated with excellent low-power performance, reaching an fmax of 40 GHz at a collector current of 10 μA. We report also a reduction in the IB-driven Early voltage for devices with small overlap due to a perimeter component of the base current, originating from the external base, or the base contact region.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126627925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Determination of the Recombination Lifetime in the Space Charge Region of MOS Field-Induced PN Junctions MOS场致PN结空间电荷区复合寿命的测定
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194820
R. Sorge, B. Heinemann, J. Grabmeier, G. Obermeier, H. Richter
{"title":"Determination of the Recombination Lifetime in the Space Charge Region of MOS Field-Induced PN Junctions","authors":"R. Sorge, B. Heinemann, J. Grabmeier, G. Obermeier, H. Richter","doi":"10.1109/ESSDERC.2000.194820","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194820","url":null,"abstract":"We report a fast and accurate method to obtain the recombination lifetime from CV measurements on MOS structures in the context of a regular CV testing. The simultaneous measurement of the gate current and the high frequency gate capacitance in the non-equilibrium nonsteady state in response to a linear gate voltage ramp, started in inversion equilibrium towards accumulation, enables the self-consistent determination of the forward current-voltage characteristic of the field-induced pn junction. The application of the model for the forward current-voltage characteristic of regular pn junctions at low minority carrier injection permits the determination of both the recombination lifetime and the energy distance of the defect centre from the midband level.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Switching Behaviour and Noise of Soft Breakdown Current in Ultra-Thin Gate Oxides 超薄栅极氧化物中软击穿电流的开关行为和噪声
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194824
A. Cester, A. Paccagnella, L. Bandiera, G. Ghidini
{"title":"Switching Behaviour and Noise of Soft Breakdown Current in Ultra-Thin Gate Oxides","authors":"A. Cester, A. Paccagnella, L. Bandiera, G. Ghidini","doi":"10.1109/ESSDERC.2000.194824","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194824","url":null,"abstract":"We studied the Soft Breakdown (SB) in ultra-thin gate oxides (< 3 nm) subjected to Constant Current Stress. SB current derives from the superposition of two Random Telegraph Signal noises with different time constants. The current noise power density follows the 1/f power law over a wide range of frequency (1 Hz 100 kHz). Moreover, the discrete fluctuations typical of SB are statistically independent events at least over time periods around hundreds of seconds, according to a Poisson process.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124212525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulation of Polysilicon Emitter Bipolar Transistors 多晶硅发射极双极晶体管的仿真
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194851
V. Palankovski, T. Grasser, M. Knaipp, S. Selberherr
{"title":"Simulation of Polysilicon Emitter Bipolar Transistors","authors":"V. Palankovski, T. Grasser, M. Knaipp, S. Selberherr","doi":"10.1109/ESSDERC.2000.194851","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194851","url":null,"abstract":"We present results of two-dimensional simulations of polysilicon emitter Bipolar Junction Transistors (BJTs). For that purpose proper polysilicon contact models have been implemented in our two-dimensional simulator MINIMOS-NT. By accounting for self-heating effects a good agreement between simulated and measured forward and output device characteristics is achieved.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133679592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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