Area-Efficient ESD Protection Design without Additional Process Cost in 0.18 um Salicided CMOS Technology

Abstract

For the electrostatic discharge (ESD) protection design in deep-submicron CMOS technologies, it is desirable to develop ESD protection devices which can be fabricated without additional photo-masks and processes. And it is required to minimize the layout area of ESD protection circuits. In this work, we propose a new lateral silicon controlled rectifier (SCR) device as an ESD protection element, and propose area-efficient ESD protection circuits. The protection circuits can be made without any additional process in advanced salicided