On a Novel Technique for the Electrical Characterization of Polycrystalline Silicon

The aim of this work is to evaluate the ability of a SOI pseudo-MOS-like technique to be tailored for polycrystalline silicon, in order to perform in situ bare material electrical characterization. The proposed technique and associated simple MOS-like models are validated on advanced, very narrow (down to 0.1μm width, i.e. less than grain size), fourcontact device geometries, for which few series-connected grains can be assumed. For the first time measurements of 1/f noise in pseudo-MOS operation are presented.