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Optimization of extension doping technology for roll-off suppression of industrial 0.1-um pMOSFETs 工业0.1 um pmosfet滚降抑制扩展掺杂技术的优化
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194799
D. Lenoble, E. Josse, A. Grouillet, C. Julien, T. Skotnicki, S. Walther, R. Liebert
{"title":"Optimization of extension doping technology for roll-off suppression of industrial 0.1-um pMOSFETs","authors":"D. Lenoble, E. Josse, A. Grouillet, C. Julien, T. Skotnicki, S. Walther, R. Liebert","doi":"10.1109/ESSDERC.2000.194799","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194799","url":null,"abstract":"For the very first time, low biased PLAD technique was integrated in an industrial 0.1-μm pMOSFET process fabrication. The electrical results emphasize that an optimized PLAD process could overcome the limitations of the conventional ion implantation technique for the fabrication of the ultra-shallow P/N junctions required by the future CMOS technology.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130433221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Adaptation of "Drain Current Charge Pumping Technique" for Interface Trap Characterization in Short Channel MOS Transistors “漏极电流电荷泵送技术”在短沟道MOS晶体管界面陷阱表征中的应用
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194778
W. Fikry, M. Ragheb, H. Haddara
{"title":"Adaptation of \"Drain Current Charge Pumping Technique\" for Interface Trap Characterization in Short Channel MOS Transistors","authors":"W. Fikry, M. Ragheb, H. Haddara","doi":"10.1109/ESSDERC.2000.194778","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194778","url":null,"abstract":"A recent characterization technique, ′′Drain Current Charge Pumping method (DCCP)′′, is modified for modelling the interface traps density, by taking into account the mobility degradation and parasitic series resistance. Such modification makes the technique applicable for both long and short channel devices. The extracted interface trap density is compared with results obtained using the classical charge pumping and the capacitance methods.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132544604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Incorporation of Equipment Simulation into Integrated Feature Scale Profile Evolution 装备仿真与综合特征尺度轮廓演化的结合
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194744
W. Pyka, S. Selberherr, V. Sukharev
{"title":"Incorporation of Equipment Simulation into Integrated Feature Scale Profile Evolution","authors":"W. Pyka, S. Selberherr, V. Sukharev","doi":"10.1109/ESSDERC.2000.194744","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194744","url":null,"abstract":"We present three-dimensional linked reactor/feature scale simulations for integrated PVD/CVD deposition sequences applied to metal stack plug-fills. Monte-Carlo particle distributions as well as CVD equipment simulations have been incorporated into threedimensional profile evolution.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Gate Oxide Thickness Scaling on Hot-Carrier Degradation in Deep-sub-micron nMOSFETs 栅极氧化物厚度缩放对深亚微米nmosfet热载子降解的影响
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194732
K. Anil, T. Pompl, I. Eisele
{"title":"Impact of Gate Oxide Thickness Scaling on Hot-Carrier Degradation in Deep-sub-micron nMOSFETs","authors":"K. Anil, T. Pompl, I. Eisele","doi":"10.1109/ESSDERC.2000.194732","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194732","url":null,"abstract":"Infiuence of oxide thickness on hotcarrier investigation criterion are investigated for drain voltages down to 0.85V. In particular we have investigated the dependence of (a) gate bias condition for peak substrate current (b) bias conditions that permit the continued use of lucky electron model for life time prediction and (c) the worst case degradation condition, on the gate oxide thickness. The worst case degradation condition was found to change from V =V /2 to peak substrate current as the oxide thickness was reduced from 5nm to 3nm and also the 3nm oxide showed higher degradation. This change is attributed to the enhanced transverse electric field and the consequent change in the type of the hot-carrier that cause the interface damage from electron to hole.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133115983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Contribution of interface traps to valence band electron tunneling in PMOS devices 界面陷阱对PMOS器件中价带电子隧穿的贡献
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194772
T. Pompl, M. Kerber, H. Wurzer, I. Eisele
{"title":"Contribution of interface traps to valence band electron tunneling in PMOS devices","authors":"T. Pompl, M. Kerber, H. Wurzer, I. Eisele","doi":"10.1109/ESSDERC.2000.194772","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194772","url":null,"abstract":"The I-V characteristic of the negatively biased p-poly PMOS changes from near valence band electron injection to near conduction band electron injection. The Fermi level is the reference energy level for valence band electron tunneling rather than the valence band edge, which results in a voltage dependent barrier height. The proposed Interface State Injection Model explains this by electron injection from interface states, quickly recharged by band to trap tunneling due to the small depletion layer width in highly doped gate material.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133320024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Macro Model for Flash EEPROM Cells 闪存EEPROM单元的宏模型
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194787
M. O’Shea, A. Concannon, K. McCarthy, B. Lane, A. Mathewson, M. Slotboom
{"title":"Macro Model for Flash EEPROM Cells","authors":"M. O’Shea, A. Concannon, K. McCarthy, B. Lane, A. Mathewson, M. Slotboom","doi":"10.1109/ESSDERC.2000.194787","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194787","url":null,"abstract":"An accurate, numerically efficient model for the transient and DC characteristics of Fowler Nordheim based flash EEPROM cells has been developed. This type of model will allow designers to efficiently and competently embed flash memory into their designs.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131953019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis of the Emitter Charge Storage in SiGe Heterojunction Bipolar Transistors with a Lightly Doped Emitter 轻掺杂SiGe异质结双极晶体管发射极电荷存储分析
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194841
L.C.M. van den Oever, L. Nanver, J. Slotboom
{"title":"Analysis of the Emitter Charge Storage in SiGe Heterojunction Bipolar Transistors with a Lightly Doped Emitter","authors":"L.C.M. van den Oever, L. Nanver, J. Slotboom","doi":"10.1109/ESSDERC.2000.194841","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194841","url":null,"abstract":"An analysis is presented of the emitter charge storage in SiGe HBTs with a lightly doped emitter (LDE) and the mechanisms that lead to the experimentally observed reduction of the fT are identified. The charge storage in the LDE is important for doping concentrations below 3×10 cm and scales with the thickness. It also depends on the Gummel number of the base and the doping concentration of the collector epilayer. For LDE concentrations below 10 cm and collector currents above 10 A/cm the gradient of the hole distribution can even become negative and cause excessive charge storage. However, under very high injection – beyond the fT,max the LDE storage decreases which gives a second peak in the fT characteristics. In order to achieve the maximum fT, the LDE must be thin (≤ 50 nm) and highly doped (≥ 3×10 cm).","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Capacitance Enhancement by Mesopore Formation for sub 100nm Deep Trench DRAM Technology 亚100nm深沟槽DRAM技术中孔形成的电容增强
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194749
A. Birner, M. Franosch, M. Goldbach, V. Lehmann, D. Schumann
{"title":"Capacitance Enhancement by Mesopore Formation for sub 100nm Deep Trench DRAM Technology","authors":"A. Birner, M. Franosch, M. Goldbach, V. Lehmann, D. Schumann","doi":"10.1109/ESSDERC.2000.194749","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194749","url":null,"abstract":"We have successfully applied the electro-chemical method of mesopore formation in deep trenches (DTs) to increase the surface of deep-trench capacitors for DRAMs. The length of the mesopores is controlled by the etching time and was up to 60 nm. Subsequently, the diameter of the mesopores, was increased to above 20 nm by an isotropic wet etch. By sufficient tuning of the arsenic doping concentration of the trench side-walls, the density of the mesopores was adjusted to 400/μm2. Thus, a surface area increase of the DTs of up to 150% was achieved.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114686005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Deactivation Phenomenon for 0.18um Technology Indium Channel NMOS Devices 0.18um工艺铟通道NMOS器件的失活现象
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194725
H. Puchner, S. Aronowitz, V. Zubkov
{"title":"Deactivation Phenomenon for 0.18um Technology Indium Channel NMOS Devices","authors":"H. Puchner, S. Aronowitz, V. Zubkov","doi":"10.1109/ESSDERC.2000.194725","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194725","url":null,"abstract":"We present experimental as well as simulation data which ehibits a deactivation phenomenon of Indium in the low dose regime. We used Indium to fabricate super-steep retrograde channel profiles for a state-ofthe-art CMOS technology. By introduction of a specific combination of dopants Indium exhibits an unexpected deactivation phenomenon which could be verified experimentally as well as by using quantumchemical simulation tools. It was found that the combination of Indium, Boron and Nitrogen in the channel region causes severe deactivation and an increase in channel dose was ineffective to raise the threshold voltage.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114877308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electrical Characterisation of Gate Dielectrics Deposited with Multipolar Electron Cyclotron Resonance Plasma Source 多极电子回旋共振等离子体源沉积栅极介质的电学特性
30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194805
G. Isai, A. Kovalgin, J. Holleman, P. Woerlee, H. Wallinga, C. Cobianu
{"title":"Electrical Characterisation of Gate Dielectrics Deposited with Multipolar Electron Cyclotron Resonance Plasma Source","authors":"G. Isai, A. Kovalgin, J. Holleman, P. Woerlee, H. Wallinga, C. Cobianu","doi":"10.1109/ESSDERC.2000.194805","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194805","url":null,"abstract":"Silicon oxide films have been deposited by plasma-enhanced chemical vapour deposition, at glass compatible temperatures. A multipolar electron cyclotron resonance plasma (ECR) source with SiH4/He and N2O was used. The electrical properties of the films were determined by means of C-V and I-V measurements. The dependencies of the electrical properties on gas-flow ratio and pressure were investigated. Critical electric fields as high as 6 MV/cm and net oxide charge densities as low as 1×1011 ions/cm2 have been obtained for the optimal deposition conditions. The oxide integrity versus CVD conditions was investigated by charge to breakdown measurements. MOSFETs have been fabricated in order to test the dielectric quality.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125002906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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