Optimization of extension doping technology for roll-off suppression of industrial 0.1-um pMOSFETs

Abstract

For the very first time, low biased PLAD technique was integrated in an industrial 0.1-μm pMOSFET process fabrication. The electrical results emphasize that an optimized PLAD process could overcome the limitations of the conventional ion implantation technique for the fabrication of the ultra-shallow P/N junctions required by the future CMOS technology.