工业0.1 um pmosfet滚降抑制扩展掺杂技术的优化

30th European Solid-State Device Research Conference Pub Date : 2000-09-11 DOI:10.1109/ESSDERC.2000.194799

D. Lenoble, E. Josse, A. Grouillet, C. Julien, T. Skotnicki, S. Walther, R. Liebert

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引用次数: 1

摘要

首次将低偏置PLAD技术集成到工业0.1 μm pMOSFET工艺制造中。电学结果强调，优化的PLAD工艺可以克服传统离子注入技术的局限性，用于制造未来CMOS技术所需的超浅P/N结。

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Optimization of extension doping technology for roll-off suppression of industrial 0.1-um pMOSFETs

For the very first time, low biased PLAD technique was integrated in an industrial 0.1-μm pMOSFET process fabrication. The electrical results emphasize that an optimized PLAD process could overcome the limitations of the conventional ion implantation technique for the fabrication of the ultra-shallow P/N junctions required by the future CMOS technology.

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来源期刊

30th European Solid-State Device Research Conference

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