Subthreshold hump mechanisms for both surface and buried channel MOSFET using STI technology

Abstract

The fundamental differences between buried-channel (BC) and surface-channel (SC) devices adopting shallow trench isolation (STI) technology are studied by using silicon data and 2D process/device simulation. For wafers with intentionally enhanced STI divots, the well-known STI induced double-hump is extensively observed for SC NMOS devices. However, BC PMOS devices keep from double-hump for all splits. The 2D simulation contours reveal that for BC PMOS devices, the corner filed crowding accelerates the depletion of holes in the BC near the STI top corner. Furthermore, the worsen segregation of counter-doped impurities near STI top corner leads to a higher magnitude of local threshold voltage associated with the corner devices.