{"title":"用等离子体氧化形成栅氧化物的n沟道和p沟道SiGe mosfet的电学特性","authors":"L. Riley, S. Hall, J. Zhang, B. Gallas, A. Evans","doi":"10.1109/ESSDERC.2000.194809","DOIUrl":null,"url":null,"abstract":"Surface channel strained SiGe MOSFETs have been fabricated using a low thermal budget process including gate oxidation by plasma anodisation at circa 100C. The fabrication process is detailed together with electrical characterisation of n and plong channel mosfets and the first 0.1μm LDD SiGe nMOSFETs. Limited increased mobilities for buried channel transistors and reduced ones for surface channel mosfets are apparent.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Electrical characterisation of n and p-channel SiGe MOSFETs with gate oxides formed by plasma oxidation\",\"authors\":\"L. Riley, S. Hall, J. Zhang, B. Gallas, A. Evans\",\"doi\":\"10.1109/ESSDERC.2000.194809\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Surface channel strained SiGe MOSFETs have been fabricated using a low thermal budget process including gate oxidation by plasma anodisation at circa 100C. The fabrication process is detailed together with electrical characterisation of n and plong channel mosfets and the first 0.1μm LDD SiGe nMOSFETs. Limited increased mobilities for buried channel transistors and reduced ones for surface channel mosfets are apparent.\",\"PeriodicalId\":354721,\"journal\":{\"name\":\"30th European Solid-State Device Research Conference\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"30th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2000.194809\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"30th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2000.194809","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electrical characterisation of n and p-channel SiGe MOSFETs with gate oxides formed by plasma oxidation
Surface channel strained SiGe MOSFETs have been fabricated using a low thermal budget process including gate oxidation by plasma anodisation at circa 100C. The fabrication process is detailed together with electrical characterisation of n and plong channel mosfets and the first 0.1μm LDD SiGe nMOSFETs. Limited increased mobilities for buried channel transistors and reduced ones for surface channel mosfets are apparent.
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