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11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)最新文献

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Low on-resistance lateral U-gate MOSFET with DSS pattern layout 低导通电阻横向u型栅极MOSFET与DSS模式布局
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764097
Y. Shimoida, Y. Hayami, K. Ohta, M. Hoshi, T. Shinohara
{"title":"Low on-resistance lateral U-gate MOSFET with DSS pattern layout","authors":"Y. Shimoida, Y. Hayami, K. Ohta, M. Hoshi, T. Shinohara","doi":"10.1109/ISPSD.1999.764097","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764097","url":null,"abstract":"This paper describes a low on-resistance lateral U-gate MOSFET having a DSS (drain window surrounded by source windows) pattern layout with TDRs (trench drain rings). The DSS pattern layout is effective in increasing the source cell density (Hoshi et al, 1995). The TDRs, which are filled with highly N/sup +/ doped polysilicon, shrink the drain cell size and reduce the resistance of the sinkers. Specific on-resistance of 0.38 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 44 V is obtained.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115002185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new current measuring principle for power electronic applications 一种新的电力电子电流测量原理
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764117
N. Karrer, P. Hofer-Noser
{"title":"A new current measuring principle for power electronic applications","authors":"N. Karrer, P. Hofer-Noser","doi":"10.1109/ISPSD.1999.764117","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764117","url":null,"abstract":"A new isolated current measurement principle named HOKA is presented. A current probe based on this principle has been realized. It was designed for a current rating of 200 A. The probe incorporates two different sensors: a Hall sensor and an air coil. DC currents of 200 A as well as transients with a di/dt of 2.5 kA//spl mu/s have been measured with a relative error of 5%.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115278910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Static and dynamic thermal characteristics of IGBT power modules IGBT电源模块的静态和动态热特性
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764037
C. Yun, P. Regli, J. Waldmeyer, W. Fichtner
{"title":"Static and dynamic thermal characteristics of IGBT power modules","authors":"C. Yun, P. Regli, J. Waldmeyer, W. Fichtner","doi":"10.1109/ISPSD.1999.764037","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764037","url":null,"abstract":"This paper discusses the thermal behavior of an IGBT power module under static and dynamic conditions. Thermal interference and solder size effects were investigated. In the dynamic response, the thermal impedance was characterized by two transition times. For a pulse width modulation (PWM) scheme, conduction and switching losses are considered and a RC component model is proposed to predict the thermal characteristics in steady state periodic condition.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127428544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Split gate MOSFET in BiCMOS power technology for logic level gate voltage application 分栅MOSFET在BiCMOS电源技术中用于逻辑电平栅电压的应用
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764061
C. Tsai, T. Efland, S. Pendharkar
{"title":"Split gate MOSFET in BiCMOS power technology for logic level gate voltage application","authors":"C. Tsai, T. Efland, S. Pendharkar","doi":"10.1109/ISPSD.1999.764061","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764061","url":null,"abstract":"Utilizing dual gate BiCMOS power technology (BPT), split gate oxide LDMOS and CMOS structures have been fabricated. These structures take advantage of low on-state channel resistance under the thin gate oxide at the source side and high breakdown voltage under the thick gate oxide at the drain side. Device simulation shows performance improvement in both R/sub ds-on/ at low V/sub gs/ and a reduction in field crowding in the reverse blocking state. Experimental characterization proves more efficient transistors can be integrated utilizing dual gate oxide at logic level gate drive while maintaining high breakdown voltage compared with single gate oxide devices.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127267483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
600 V power conversion system-on-a-chip based on thin layer silicon-on-insulator 基于薄层绝缘体上硅的600v功率转换片上系统
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764126
T. Letavic, M. Simpson, E. Arnold, E. Peters, R. Aquino, J. Curcio, S. Herko, Swarnava Mukherjee
{"title":"600 V power conversion system-on-a-chip based on thin layer silicon-on-insulator","authors":"T. Letavic, M. Simpson, E. Arnold, E. Peters, R. Aquino, J. Curcio, S. Herko, Swarnava Mukherjee","doi":"10.1109/ISPSD.1999.764126","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764126","url":null,"abstract":"An integrated 600 V power conversion system is described based on smart power technology which combines novel lateral high-voltage RESURF transistor structures and a merged bipolar/CMOS/DMOS process flow on thin-layer SOI substrates. A new high-voltage SOI LDMOS device structure is presented which results in a factor-of-two decrease in specific on-resistance and a factor-of-two improvement in source-follower saturated current, thus overcoming a key limitation of integrated thin-layer technology. This opens new application areas for thin-layer SOI, such as lighting electronics, power modules, motor control, and others, a significant development for the integration of power conversion systems.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Predicted electrical characteristics of 4500 V super multi-RESURF MOSFETs 预测了4500v超级多路复用mosfet的电特性
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764066
Y. Kawaguchi, K. Nakamura, A. Yahata, A. Nakagawa
{"title":"Predicted electrical characteristics of 4500 V super multi-RESURF MOSFETs","authors":"Y. Kawaguchi, K. Nakamura, A. Yahata, A. Nakagawa","doi":"10.1109/ISPSD.1999.764066","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764066","url":null,"abstract":"In this paper, we show the optimized device parameters for various voltage multi-RESURF devices based on exact simulation. In addition, we also present, for the first time, the exact static and transient simulation of a 4500 V multi-RESURF device. The distinguishing feature of the multi-RESURF MOSFET is that a storage time exists and that the fall time is extremely small. The multi-RESURF MOSFET was found to be an ideal device for high voltage applications, superior to IGBTs.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115793693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Large reverse biased safe operating area for a low loss HiGT 大反向偏置安全操作区域为低损耗高
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764044
Y. Uchino, H. Kobayashi, M. Mori, R. Saito
{"title":"Large reverse biased safe operating area for a low loss HiGT","authors":"Y. Uchino, H. Kobayashi, M. Mori, R. Saito","doi":"10.1109/ISPSD.1999.764044","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764044","url":null,"abstract":"A high conductivity IGBT (HiGT) with a reverse biased safe operating area (RBSOA) as large as that of a conventional IGBT has been presented. The fabricated HiGT has a rated current of 50 A and a blocking capability of 3.3 kV. Optimizing the concentration of impurities in the hole carrier layer enabled the HiGT to turn off a current twice the rated current by applying 2200 V, which is the maximum voltage of the 1500 V line. This large RBSOA was maintained while achieving a short circuit capability and a better trade-off relation between the collect-emitter saturation voltage (V/sub CE(sat)/) and the turn-off loss. The V/sub CE(sat)/ of this optimized HiGT was 1.3 V lower than that of a conventional IGBT. The turn-off loss, short circuit capability, and static and dynamic avalanche voltages were equivalent to those of a conventional IGBT.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
4.5 kV-fast-diodes with expanded SOA using a multi-energy proton lifetime control technique 使用多能质子寿命控制技术的扩展SOA的4.5 kv快速二极管
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764078
O. Humbel, N. Galster, F. Bauer, W. Fichtner
{"title":"4.5 kV-fast-diodes with expanded SOA using a multi-energy proton lifetime control technique","authors":"O. Humbel, N. Galster, F. Bauer, W. Fichtner","doi":"10.1109/ISPSD.1999.764078","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764078","url":null,"abstract":"This paper presents a 4.5 kV diode fabricated using a new ion irradiation technique whereby electrons are replaced by protons in a second irradiation step. The second proton peak is located close to the middle of the n-base. Compared to the combined ion-electron irradiation, diodes with a double proton peak show a smaller maximum reverse-recovery current and a much smoother tail current behavior. The new device has an excellent ruggedness, and is able to withstand a peak power of 1 MW/cm/sup 2/.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115865262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Efficiency of power devices using full Cu metallization technologies 全铜金属化技术对功率器件效率的影响
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764053
E. Kobori, N. Izumi, N. Kumamoto, Y. Hamazawa, M. Matsumoto, K. Yamamoto, A. Kamisawa
{"title":"Efficiency of power devices using full Cu metallization technologies","authors":"E. Kobori, N. Izumi, N. Kumamoto, Y. Hamazawa, M. Matsumoto, K. Yamamoto, A. Kamisawa","doi":"10.1109/ISPSD.1999.764053","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764053","url":null,"abstract":"This paper describes some advantages of Cu dual damascene structures for power LSI devices. By using the Cu process, a lower value of V/sub sat/ was obtained than that using Al-Si-Cu wiring. The lifetime of Cu lines was about 10 times longer than when using Al-Cu lines. The on-resistance of DMOS is reduced by as much as 31% when using the Cu process.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126739334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Submicron silicon carbide CMOS for smartpower applications 亚微米碳化硅CMOS智能电源应用
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764121
K. Kornegay
{"title":"Submicron silicon carbide CMOS for smartpower applications","authors":"K. Kornegay","doi":"10.1109/ISPSD.1999.764121","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764121","url":null,"abstract":"This paper describes the development of silicon carbide (SiC) submicron CMOS technology for smart power applications. NMOS transistors are fabricated with 0.5 /spl mu/m (drawn) channel lengths while PMOS transistors exhibit punchthrough at 0.8 /spl mu/m channel lengths. Digital logic circuits are also fabricated and exhibit nanosecond switching performance. Finally, performance limiting factors such as parasitic series resistance are also investigated.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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