{"title":"Split gate MOSFET in BiCMOS power technology for logic level gate voltage application","authors":"C. Tsai, T. Efland, S. Pendharkar","doi":"10.1109/ISPSD.1999.764061","DOIUrl":null,"url":null,"abstract":"Utilizing dual gate BiCMOS power technology (BPT), split gate oxide LDMOS and CMOS structures have been fabricated. These structures take advantage of low on-state channel resistance under the thin gate oxide at the source side and high breakdown voltage under the thick gate oxide at the drain side. Device simulation shows performance improvement in both R/sub ds-on/ at low V/sub gs/ and a reduction in field crowding in the reverse blocking state. Experimental characterization proves more efficient transistors can be integrated utilizing dual gate oxide at logic level gate drive while maintaining high breakdown voltage compared with single gate oxide devices.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1999.764061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Utilizing dual gate BiCMOS power technology (BPT), split gate oxide LDMOS and CMOS structures have been fabricated. These structures take advantage of low on-state channel resistance under the thin gate oxide at the source side and high breakdown voltage under the thick gate oxide at the drain side. Device simulation shows performance improvement in both R/sub ds-on/ at low V/sub gs/ and a reduction in field crowding in the reverse blocking state. Experimental characterization proves more efficient transistors can be integrated utilizing dual gate oxide at logic level gate drive while maintaining high breakdown voltage compared with single gate oxide devices.