Split gate MOSFET in BiCMOS power technology for logic level gate voltage application

C. Tsai, T. Efland, S. Pendharkar
{"title":"Split gate MOSFET in BiCMOS power technology for logic level gate voltage application","authors":"C. Tsai, T. Efland, S. Pendharkar","doi":"10.1109/ISPSD.1999.764061","DOIUrl":null,"url":null,"abstract":"Utilizing dual gate BiCMOS power technology (BPT), split gate oxide LDMOS and CMOS structures have been fabricated. These structures take advantage of low on-state channel resistance under the thin gate oxide at the source side and high breakdown voltage under the thick gate oxide at the drain side. Device simulation shows performance improvement in both R/sub ds-on/ at low V/sub gs/ and a reduction in field crowding in the reverse blocking state. Experimental characterization proves more efficient transistors can be integrated utilizing dual gate oxide at logic level gate drive while maintaining high breakdown voltage compared with single gate oxide devices.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1999.764061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Utilizing dual gate BiCMOS power technology (BPT), split gate oxide LDMOS and CMOS structures have been fabricated. These structures take advantage of low on-state channel resistance under the thin gate oxide at the source side and high breakdown voltage under the thick gate oxide at the drain side. Device simulation shows performance improvement in both R/sub ds-on/ at low V/sub gs/ and a reduction in field crowding in the reverse blocking state. Experimental characterization proves more efficient transistors can be integrated utilizing dual gate oxide at logic level gate drive while maintaining high breakdown voltage compared with single gate oxide devices.
分栅MOSFET在BiCMOS电源技术中用于逻辑电平栅电压的应用
利用双栅BiCMOS电源技术(BPT),制备了分栅氧化LDMOS和CMOS结构。这些结构利用了源侧薄栅氧化层下的低导通状态通道电阻和漏侧厚栅氧化层下的高击穿电压。器件仿真结果表明,低V/sub - gs/下的R/sub - ds-on/性能得到改善,反向阻塞状态下的场拥挤减少。实验证明,与单栅氧化器件相比,在逻辑级栅极驱动下使用双栅氧化器件可以集成更高效的晶体管,同时保持高击穿电压。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信