Sang Gi Kim, Jongdae Kim, Q. Song, J. Koo, D. Kim, K. Cho
{"title":"A power IC technology with excellent trench isolation and p-LDMOS transistor through tapered TEOS field oxides","authors":"Sang Gi Kim, Jongdae Kim, Q. Song, J. Koo, D. Kim, K. Cho","doi":"10.1109/ISPSD.1999.764119","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764119","url":null,"abstract":"A smart PIC technology with the reproducible tapered TEOS oxide has been proposed to reduce the fabrication process steps and obtain p-LDMOS with low on-resistance. Several process steps could be reduced, compared to the conventional process. With a similar breakdown voltage (5% reduction), the on-resistance was improved by 35% or more with the proposed structure.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124812953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Trost, R. Ridley, M.K. Khan, T. Grebs, H. Evans, S. Arthur
{"title":"The effect of charge in junction termination extension passivation dielectrics","authors":"J. Trost, R. Ridley, M.K. Khan, T. Grebs, H. Evans, S. Arthur","doi":"10.1109/ISPSD.1999.764094","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764094","url":null,"abstract":"The edge termination of the blocking junction in power devices is critical to the operation and reliability of the device. The influence of charging in the thin films used to passivate the junction termination extension (JTE) in a planar >3000 V power diode has been investigated. This study was used to develop strategies to overcome the loss of blocking capability observed after high temperature reverse bias stressing.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122078085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xu Cheng, B. Kang, J. Sin, Zhe Wang, Guozhong Li, Yu Wu
{"title":"Monolithically integrated power device consisting of a GAT and a MPS diode with increased switching speed","authors":"Xu Cheng, B. Kang, J. Sin, Zhe Wang, Guozhong Li, Yu Wu","doi":"10.1109/ISPSD.1999.764131","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764131","url":null,"abstract":"A new integrated power device structure, which puts together a gate associated transistor (GAT) and a merged pin Schottky (MPS) diode, is proposed. It is verified by simulations and experiments that the new structure has gained both the faster recovery speed of the diode and the faster switching speed of the transistor compared to that of the conventional structure consisting of a traditional power bipolar junction transistor (BJT) and a p-i-n diode. The new structure can be realized in an ordinary planar process, and the fast switching speed can be achieved at low cost without the need for special carrier-lifetime-controlling techniques such as Pt doping.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131558113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Hower, J. Lin, S. Haynie, S. Paiva, R. Shaw, N. Hepfinger
{"title":"Safe operating area considerations in LDMOS transistors","authors":"P. Hower, J. Lin, S. Haynie, S. Paiva, R. Shaw, N. Hepfinger","doi":"10.1109/ISPSD.1999.764046","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764046","url":null,"abstract":"The trade-off between breakdown voltage and on-resistance is a well-known feature of both lateral and vertical DMOS transistors. The trade-offs and restrictions imposed by the \"safe operating area\" are less familiar. The SOA defines limits on the excursion of the operating point in the I/sub d/-V/sub ds/ plane. To be correct, the SOA should also include thermal limitations; however, these can be treated separately. In this paper, we focus on the \"electrical SOA\", which is defined by a specific boundary line in the I/sub d/-V/sub ds/ plane. Although the LDMOS SOA has been discussed in a number of papers, the details of the device physics that determine the SOA boundary are still somewhat unclear and further work is needed. The main purpose of this paper is to investigate device behaviour in the neighborhood of the SOA boundary and then use these results to predict the SOA. We consider devices with and without drain extensions using a self-aligned body diffusion. The predicted SOA is shown to be in good agreement with measurements for both types of LDMOS. Current flow within the device is examined in detail. The observed SOA is shown to be consistent with the silicon power density limit, a fundamental characteristic of silicon devices. Finally, we show how a simplified two-terminal model of the drain region can be used to demonstrate the behaviour of the LDMOS as it approaches snap-back. This approach is analogous to that previously used to model the onset of avalanche initiated second breakdown in bipolar transistors (hower and Reddi, 1970).","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131626645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An improved power MOSFET using a novel split well structure","authors":"J. Zeng, C. F. Wheatley","doi":"10.1109/ISPSD.1999.764098","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764098","url":null,"abstract":"The design trade-offs between the specific on-resistance (R/sub sp/), the ruggedness and the reverse recovery charge (Q/sub rr/) of the body-diode for vertical power MOSFETs has been significantly improved by using a novel split-well (SW) concept. The implementation of the SW structure is straightforward with low cost. It is expected that the source exclusion mask can be removed. When compared to a conventional VDMOST with the same design rules, the SW device provides 15% lower R/sub sp/ and 10% lower Q/sub rr/ without degradation of device ruggedness. In addition, it is expected that the SW device will yield higher hot-carrier reliability.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129349617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power management issues for future generation microprocessors","authors":"F. Lee, Xunwei Zhou","doi":"10.1109/ISPSD.1999.764036","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764036","url":null,"abstract":"By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation of high-speed CMOS processors (e.g. Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range to further enhance their speed-power performance. These new generations of microprocessors will present very dynamic loads with high current slew rates during transients. As a result, they will require a special power supply, a voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. This paper addresses the critical technical issues to achieve this target for future generation microprocessors.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124687359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Udrea, P.R. Waind, J. Thomson, T. Trajkovic, S.S.M. Chan, S. Huang, G. Amaratunga
{"title":"1.4 kV, 25 A, PT and NPT trench IGBTs with optimum forward characteristics","authors":"F. Udrea, P.R. Waind, J. Thomson, T. Trajkovic, S.S.M. Chan, S. Huang, G. Amaratunga","doi":"10.1109/ISPSD.1999.764082","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764082","url":null,"abstract":"In this paper, we report the development of 1.4 kV 25 A punch-through (PT) and nonpunch-through (NPT) trench IGBTs with ultra-low on-resistance, latch-up free operation and highly superior overall performance when compared to previously reported DMOS IGBTs in the same class. We have fabricated both PT and transparent anode NPT devices to cover a wide range of applications which require very low on-state losses or very fast time with ultra-low switching losses. The minimum forward voltage drop at the standard current density of 100 A/cm/sup 2/ was 1.1 V for PT nonirradiated devices and 2.1 V for 16 MRad PT irradiated devices. The nonirradiated transparent emitter NPT structure has a typical forward voltage drop of 2.2 V, a turn-off time below 100 ns and turn-off energy losses of 11.2 mW/cm/sup 2/ at 125 C. The maximum controllable current density was in excess of 1000 A/cm/sup 2/.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123806187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}