A power IC technology with excellent trench isolation and p-LDMOS transistor through tapered TEOS field oxides

Abstract

A smart PIC technology with the reproducible tapered TEOS oxide has been proposed to reduce the fabrication process steps and obtain p-LDMOS with low on-resistance. Several process steps could be reduced, compared to the conventional process. With a similar breakdown voltage (5% reduction), the on-resistance was improved by 35% or more with the proposed structure.