Power management issues for future generation microprocessors

Abstract

By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation of high-speed CMOS processors (e.g. Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range to further enhance their speed-power performance. These new generations of microprocessors will present very dynamic loads with high current slew rates during transients. As a result, they will require a special power supply, a voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. This paper addresses the critical technical issues to achieve this target for future generation microprocessors.