低导通电阻横向u型栅极MOSFET与DSS模式布局

Y. Shimoida, Y. Hayami, K. Ohta, M. Hoshi, T. Shinohara
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引用次数: 2

摘要

本文描述了一种低导通电阻的横向u型栅极MOSFET,具有DSS(漏窗被源窗包围)和tdr(沟槽漏环)的模式布局。DSS模式布局在增加源单元密度方面是有效的(Hoshi et al, 1995)。tdr填充了高N/sup +/掺杂的多晶硅,缩小了漏极的尺寸,降低了沉管的阻力。比导通电阻为0.38 m/spl ω //spl middot/cm/sup 2/,阻断电压为44 V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Low on-resistance lateral U-gate MOSFET with DSS pattern layout
This paper describes a low on-resistance lateral U-gate MOSFET having a DSS (drain window surrounded by source windows) pattern layout with TDRs (trench drain rings). The DSS pattern layout is effective in increasing the source cell density (Hoshi et al, 1995). The TDRs, which are filled with highly N/sup +/ doped polysilicon, shrink the drain cell size and reduce the resistance of the sinkers. Specific on-resistance of 0.38 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 44 V is obtained.
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