Low on-resistance lateral U-gate MOSFET with DSS pattern layout

Abstract

This paper describes a low on-resistance lateral U-gate MOSFET having a DSS (drain window surrounded by source windows) pattern layout with TDRs (trench drain rings). The DSS pattern layout is effective in increasing the source cell density (Hoshi et al, 1995). The TDRs, which are filled with highly N/sup +/ doped polysilicon, shrink the drain cell size and reduce the resistance of the sinkers. Specific on-resistance of 0.38 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 44 V is obtained.