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11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)最新文献

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Explosion tests on IGBT high voltage modules IGBT高压模块的爆炸试验
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764079
S. Gekenidis, E. Ramezani, H. Zeller
{"title":"Explosion tests on IGBT high voltage modules","authors":"S. Gekenidis, E. Ramezani, H. Zeller","doi":"10.1109/ISPSD.1999.764079","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764079","url":null,"abstract":"In this paper, we report on surge current experiments with IGBT modules in low inductance, snubberless circuits. We give design guidelines for robust modules and robust converter designs, discuss scenarios of consequential damage and propose worst case test conditions for explosion safety. For wire bonded modules, the limit for material ejection is at a stored capacitive energy of about 10 kJ. In a good design, the shock wave trajectory is defined and no metallic parts obstruct the plasma expansion. The worst case damage occurs if, initially, a single chip fails. Press-pack modules can be designed to contain the plasma inside the housing in the case of a short circuit. Simple protective measures are sufficient to protect personnel.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128422029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
High-density ultra-low R/sub dson/ 30 volt N-channel trench FETs for DC/DC converter applications 用于DC/DC变换器应用的高密度超低R/sub / 30伏n沟道场效应管
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764123
R. Sodhi, R. Malik, D. Asselanis, D. Kinzer
{"title":"High-density ultra-low R/sub dson/ 30 volt N-channel trench FETs for DC/DC converter applications","authors":"R. Sodhi, R. Malik, D. Asselanis, D. Kinzer","doi":"10.1109/ISPSD.1999.764123","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764123","url":null,"abstract":"This paper presents a new high-density trench MOSFET design with ultra-low R/sub dson/ for DC/DC converter applications. A benchmark low specific on-resistance of 26 m/spl Omega/.mm/sup 2/ at 4.5 V gate bias is reported. A remote contact feature is utilized to obtain such high channel density and corresponding channel conductance. In-circuit efficiency as high as 89% is obtained, which is the best obtained in the industry to date.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125407033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A new model for dopant redistribution in a power SOI structure 功率SOI结构中掺杂物重分布的新模型
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764102
T. Ishiyama, S. Matsumoto, T. Yachi, W. Fichtner
{"title":"A new model for dopant redistribution in a power SOI structure","authors":"T. Ishiyama, S. Matsumoto, T. Yachi, W. Fichtner","doi":"10.1109/ISPSD.1999.764102","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764102","url":null,"abstract":"We propose an interlayer model of the SOI structure during annealing, that explains the phosphorus pile-up and boron segregation that occurs in the SOI structure. Simulated dopant profiles based on the model showed its usefulness in predicting the electrical characteristics of SOI power devices.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129415760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High performance extended drain MOSFETs (EDMOSFETs) with metal field plate 高性能扩展漏极mosfet (edmosfet)与金属场板
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764110
Mueng-Ryul Lee, O. Kwon
{"title":"High performance extended drain MOSFETs (EDMOSFETs) with metal field plate","authors":"Mueng-Ryul Lee, O. Kwon","doi":"10.1109/ISPSD.1999.764110","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764110","url":null,"abstract":"We propose a structure for extended drain MOSFETs (EDMOSFETs) with a metal field plate separated from the gate electrode instead of the polysilicon field plate in conventional LDMOSFETs. The specific on-resistance is improved by applying a higher voltage to the field plate than the gate voltage because of the enhanced conductivity modulation, and the breakdown voltage of 280 V is not changed by the field plate voltage. When a voltage of 50 V is applied to the field plate, the specific on-resistance of a 280 V EDMOSFET is 17.63 m/spl Omega/cm/sup 2/, which is lower than that of conventional LDMOSFETs by 11.8%. The performance of the EDMOSFETs is the best reported result in 280 V class lateral high voltage MOS devices.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129008938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A first approach on parallel-monitor integration circuit for energy-capacitor-system (ECS) 能量-电容系统(ECS)并行监控集成电路的初步研究
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764116
Y. Yamamoto, M. Horii, Y. Shinriki, M. Mitome, S. Fujimoto, H. Inoue, M. Yamagishi, M. Shinotsuka, M. Okamura
{"title":"A first approach on parallel-monitor integration circuit for energy-capacitor-system (ECS)","authors":"Y. Yamamoto, M. Horii, Y. Shinriki, M. Mitome, S. Fujimoto, H. Inoue, M. Yamagishi, M. Shinotsuka, M. Okamura","doi":"10.1109/ISPSD.1999.764116","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764116","url":null,"abstract":"A novel integrated circuit has been developed for a high efficiency electric power storage system, called the energy-capacitor-system. The integrated circuit mainly acts as a voltage-regulator to protect electric-double-layer capacitors from overcharging. The clump-voltage of the IC is 2.6 V and its temperature coefficient is 0.05 mV/deg. The developed IC can be successfully applied to the energy capacitor system.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131888283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A planarized high-voltage silicon trench sidewall oxide-merged PIN/Schottky (TSOX-MPS) rectifier 一种平面化高压硅沟槽侧壁氧化合并PIN/肖特基(TSOX-MPS)整流器
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764077
R.N. Gupta, W. Min, T. Chow, H. Chang, C. Winterhalter
{"title":"A planarized high-voltage silicon trench sidewall oxide-merged PIN/Schottky (TSOX-MPS) rectifier","authors":"R.N. Gupta, W. Min, T. Chow, H. Chang, C. Winterhalter","doi":"10.1109/ISPSD.1999.764077","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764077","url":null,"abstract":"A new trench junction rectifier, which uses sidewall oxide spacers to separate the main PIN region from the adjacent Schottky regions, is described. The Schottky regions help remove minority carriers from the drift region during turn off and facilitate forward conduction in the on-state. Simulations and experimental measurements have shown that the peak reverse current and reverse recovery charge are significantly improved along with a lower forward voltage drop when compared to the conventional P/sup +/IN rectifier.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131996140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Lateral dual channel emitter switched thyristor employing segmented p-base 采用分段p基的横向双通道发射极开关晶闸管
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764100
D. Byeon, J. Oh, M. Han, Y. Choi
{"title":"Lateral dual channel emitter switched thyristor employing segmented p-base","authors":"D. Byeon, J. Oh, M. Han, Y. Choi","doi":"10.1109/ISPSD.1999.764100","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764100","url":null,"abstract":"A new lateral dual channel emitter switched thyristor employing segmented p-base, entitled the lateral SB-DCEST, is proposed in order to eliminate the snap-back and to decrease the forward voltage drop. The forward I-V characteristics of the fabricated lateral SB-DCEST show that the snap-back problem is almost eliminated and a lower forward voltage drop by 1 V is obtained when compared with the conventional lateral DCEST due to the enhanced thyristor operation.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Properties of CoolMOS/sup TM/ between 420 K and 80 K-the ideal device for cryogenic applications CoolMOS/sup TM/在420 K和80 K之间的性能-低温应用的理想设备
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764063
A. Schlogl, G. Deboy, H. W. Lorenzen, U. Linnert, H. Schulze, J. Stengl
{"title":"Properties of CoolMOS/sup TM/ between 420 K and 80 K-the ideal device for cryogenic applications","authors":"A. Schlogl, G. Deboy, H. W. Lorenzen, U. Linnert, H. Schulze, J. Stengl","doi":"10.1109/ISPSD.1999.764063","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764063","url":null,"abstract":"The electrical properties of CoolMOS/sup TM/, the first representative of a new generation of power MOSFETs, based on the concept of charge compensation, were investigated at temperatures between 80 K and 423 K. Since it unifies all the advantages of MOSFETs, where additionally higher current densities are possible, the device is not only very attractive for power electronic systems at ambient temperatures, but also for cryogenic temperatures T>77 K.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114973131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A new high-voltage integrated switch: the "thyristor dual" function 一种新型高压集成开关:“晶闸管双通”功能
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764086
J. Sanchez, M. Breil, P. Austin, J. Laur, J. Jalade, B. Rousset, H. Foch
{"title":"A new high-voltage integrated switch: the \"thyristor dual\" function","authors":"J. Sanchez, M. Breil, P. Austin, J. Laur, J. Jalade, B. Rousset, H. Foch","doi":"10.1109/ISPSD.1999.764086","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764086","url":null,"abstract":"In this paper, a new monolithic integrated device providing the \"thyristor dual\" function without auxiliary supply and based on the functional integration mode is investigated. The influence of the physical and technological parameters of this new structure upon the main electrical characteristics and the physical behaviour has been analyzed using the ATLAS software tool. An optimized device is proposed and test structures have been fabricated.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131968233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
RF LDMOSFET with graded gate structure 具有梯度栅极结构的RF LDMOSFET
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) Pub Date : 1999-05-26 DOI: 10.1109/ISPSD.1999.764103
Shuming Xu, P. Foo
{"title":"RF LDMOSFET with graded gate structure","authors":"Shuming Xu, P. Foo","doi":"10.1109/ISPSD.1999.764103","DOIUrl":"https://doi.org/10.1109/ISPSD.1999.764103","url":null,"abstract":"This paper describes a new RF LDMOS with a graded structure. It enables a very thin gate oxide to be used in the channel region to achieve high transconductance, but at the gate edges, the polysilicon is lifted off to more than 3 times that thickness, and thus the parasitic capacitance values C/sub gd/ and C/sub gs/ are significantly reduced. This improves the RF output power, gain and the cut-off frequency. Due to the release of the electric field in the gate edge, a sufficiently high breakdown voltage can be realized with very thin gate oxide.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131799438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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