E. Kobori, N. Izumi, N. Kumamoto, Y. Hamazawa, M. Matsumoto, K. Yamamoto, A. Kamisawa
{"title":"Efficiency of power devices using full Cu metallization technologies","authors":"E. Kobori, N. Izumi, N. Kumamoto, Y. Hamazawa, M. Matsumoto, K. Yamamoto, A. Kamisawa","doi":"10.1109/ISPSD.1999.764053","DOIUrl":null,"url":null,"abstract":"This paper describes some advantages of Cu dual damascene structures for power LSI devices. By using the Cu process, a lower value of V/sub sat/ was obtained than that using Al-Si-Cu wiring. The lifetime of Cu lines was about 10 times longer than when using Al-Cu lines. The on-resistance of DMOS is reduced by as much as 31% when using the Cu process.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1999.764053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper describes some advantages of Cu dual damascene structures for power LSI devices. By using the Cu process, a lower value of V/sub sat/ was obtained than that using Al-Si-Cu wiring. The lifetime of Cu lines was about 10 times longer than when using Al-Cu lines. The on-resistance of DMOS is reduced by as much as 31% when using the Cu process.