2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)最新文献

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Fabrication and characterization of Al/sub x/Ga/sub 1-x/N/GaN heterostructures with high mobility of two-dimensional electron gas 高迁移率二维电子气体Al/sub x/Ga/sub 1-x/N/GaN异质结构的制备与表征
B. Shen, Y.G. Zhou, Z. Zheng, J. Liu, H.M. Zhou, Y. Qian, R. Zhang, Y. Shi, Y.D. Zheng
{"title":"Fabrication and characterization of Al/sub x/Ga/sub 1-x/N/GaN heterostructures with high mobility of two-dimensional electron gas","authors":"B. Shen, Y.G. Zhou, Z. Zheng, J. Liu, H.M. Zhou, Y. Qian, R. Zhang, Y. Shi, Y.D. Zheng","doi":"10.1109/ICSICT.2001.982112","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982112","url":null,"abstract":"Modulation-doped Al/sub 0.22/Ga/sub 0.78/N/GaN heterostructures with different Al/sub 0.22/Ga/sub 0.78/N barrier thickness were grown by means of metal-organic chemical vapor deposition. The Al/sub 0.22/Ga/sub 0.78/N layer is still pseudomorphic growth when its thickness is 53 nm. The mobility of the two dimensional electron gas (2DEG) at the heterointerfaces is much higher than that of the electrons in GaN films at both 300 K and 77 K. The dramatic decrease of the 2DEG mobility in an Al/sub 0.22/Ga/sub 0.78/N/GaN heterostructure corresponds to the partial relaxation of the Al/sub 0.22/Ga/sub 0.78/N barrier.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115642966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gate width optimization of PHEMT MMIC LNA for low power consumption 低功耗PHEMT MMIC LNA的门宽优化
J. Yuk, Byoung Gun Choi, You Sang Lee, C. Park
{"title":"Gate width optimization of PHEMT MMIC LNA for low power consumption","authors":"J. Yuk, Byoung Gun Choi, You Sang Lee, C. Park","doi":"10.1109/ICSICT.2001.982146","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982146","url":null,"abstract":"We have developed C-band LNAs of a very low noise and of a very low power dissipation by using a commercially standard 0.25 /spl mu/m T gate PHEMT technology. A 2-stage MMIC LNA of very low noise figure as low as 0.76 dB and gain of 16 dB at 5.4 GHz has been implemented using a minimum input matching network. Also an LNA of very low power consumption as small as 18 mW with 3 V power supply has been implemented using an optimization of gate width and circuit topology.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121370105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ferroelectric dielectric technology 铁电介质技术
H. Nozawa, M. Takayama, S. Koyama
{"title":"Ferroelectric dielectric technology","authors":"H. Nozawa, M. Takayama, S. Koyama","doi":"10.1109/ICSICT.2001.981597","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981597","url":null,"abstract":"Ferroelectric thin film, which is a kind of functional dielectric, especially provided with hysteresis characteristics in P-E curve, has drawn wide attention in the LSI field, because of its ideal features, like nonvolatility and fast programming operation at low voltage. From various points of view, for example, academic, industry and so on, basic studies have been drastically advanced for this decade. Recently, ferroelectric memory, called FeRAM, succeeds practically in volume production. At this stage, interestis in the theoretical prediction of life of the products and their application to logic devices. This paper has described a leading study on reliability physics and some applications of ferroelectric dielectric technology. Finally promising perspectives on the ferroelectric dielectric technology are shown.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131283063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A compact serial RF MEMS switch for S-band application 一个紧凑的串行射频MEMS开关s波段应用
H. Xiaodong, Lumiao, Hou Maohui, He Qingguo, Gao Cuizhuo, Bai Xiwei, Zhao Zhengping
{"title":"A compact serial RF MEMS switch for S-band application","authors":"H. Xiaodong, Lumiao, Hou Maohui, He Qingguo, Gao Cuizhuo, Bai Xiwei, Zhao Zhengping","doi":"10.1109/ICSICT.2001.981999","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981999","url":null,"abstract":"This paper reviews the recent progress in MEMS for radio frequency (RF) switches. Several structures were designed, fabricated and tested in the background of S-band application. Among these structures a compact serial switch was presented in detail. The performance of 21.0 dB isolation and 0.5 dB insertion loss was demonstrated in a HP 85 10A vector Network Analyzer while mounted on a rf carrier.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131417067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel RESURF LDMOS with embedded CB-layer 一种新型嵌入cb层的重熔LDMOS
Junjie Xie, Yan Han
{"title":"A novel RESURF LDMOS with embedded CB-layer","authors":"Junjie Xie, Yan Han","doi":"10.1109/ICSICT.2001.981450","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981450","url":null,"abstract":"RESURF LDMOS resorts to lightly doping in the drift region to improve the breakdown voltage which inevitably increases the on-resistance. Here, a novel voltage-sustaining layer called the composite buffer layer (CB-layer for short) is proposed to be embedded in the RESURF LDMOS which significantly reduces the on-resistance, and the breakdown voltage is still high. The CB-layer consists of one n- and p-type layer, both of which are heavier doped to provide a good conductive channel for the carriers in the on-state. When the drift region is fully depleted in the off-state the whole residual charges in the CB-layer approximates to zero since they cancel each other out which means a high breakdown voltage is sustained.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131505576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Hybrid inverter circuits of nano-MOSFET and metallic-based SET 纳米mosfet与金属基SET的混合逆变电路
J. Cheng, J. Jiang, Q. Cai
{"title":"Hybrid inverter circuits of nano-MOSFET and metallic-based SET","authors":"J. Cheng, J. Jiang, Q. Cai","doi":"10.1109/ICSICT.2001.982160","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982160","url":null,"abstract":"In this paper, we give a novel choice of nanometer scale inverter. It is based on a nano-MOSFET as a drive transistor and a metallic-based SET (single electron transistor) as a load. The nano-MOSFET is assumed to have intrinsic silicon channel and metal source/drain. Applying a simple method based on ballistic transportation, the device characteristics can be determined. On the other hand, SET, the device operating on the principle of Coulomb blockade effects, can be realized on a metallic base. By connecting the SET gate to its source, we can treat it as a normal resistance. Our simulation proved the two devices cooperated very well and we got the ideal characteristics of this inverter. These results are then compared with another form of inverter that we presented previously, and we conclude the advantages of both circuits at the end of the paper.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A scaleable metal-insulator-metal capacitors process for 0.35 to 0.18 /spl mu/m analog and RFCMOS 一种可扩展的金属-绝缘体-金属电容器工艺,用于0.35至0.18 /spl μ m模拟和RFCMOS
K. Shao, S. Chu, K. Chew, Guan-Ping Wu, C. Ng, N. Tan, B. Shen, A. Yin, Zhe Zheng
{"title":"A scaleable metal-insulator-metal capacitors process for 0.35 to 0.18 /spl mu/m analog and RFCMOS","authors":"K. Shao, S. Chu, K. Chew, Guan-Ping Wu, C. Ng, N. Tan, B. Shen, A. Yin, Zhe Zheng","doi":"10.1109/ICSICT.2001.981465","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981465","url":null,"abstract":"Two different material plates used for a high density metal-insulator-metal (MIM) capacitor (1.0 fF//spl mu/m/sup 2/) top plate are studied. The two MIM capacitor process differences are compared. Their processes are very compatible with standard logic processes, and can be easily integrated into 0.35 /spl mu/m down to 0.18 /spl mu/m AlCu interconnection BEOL process. Both demonstrated good DC electrical parameter results. Their temperature, voltage coefficient and matching data fit meet the needs of most analog designers. A Q value >80 at 2.45 GHz was also achieved from the RF measurement.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128120147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An IC chip of magneto-sensitive silicon transistors sensor 一种磁敏硅晶体管传感器IC芯片
Dianzhong Wen
{"title":"An IC chip of magneto-sensitive silicon transistors sensor","authors":"Dianzhong Wen","doi":"10.1109/ICSICT.2001.982024","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982024","url":null,"abstract":"A new type differential structure of double-injection long-base magnetic-sensitive Si transistors are the basis of magnetic field sensors. The IC chip of magnetic-sensitive transistors is deigned and the integrated circuit switches from a 1 level to a 0 level when the magnetic-sensitive transistors generator experiences a field level of 400 G. The Schmitt trigger section prevents turn on of the 1 level until the field falls back below 200 G. Such chips may be used as part of Hall effect keyboards to avoid the contact bounce effects of mechanical switches. The IC magnetic-sensitive transistor sensor was fabricated using the poly-silicon epitaxial and VMOS technology.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133447318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Ultra shallow secondary ion mass spectrometry 超浅次离子质谱法
R. Liu, C. M. Ng, A. Wee
{"title":"Ultra shallow secondary ion mass spectrometry","authors":"R. Liu, C. M. Ng, A. Wee","doi":"10.1109/ICSICT.2001.982073","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982073","url":null,"abstract":"Following the increasingly stringent requirements in the characterization of sub-micron IC devices, a good understanding of the various factors affecting ultra shallow depth profiling in secondary ion mass spectrometry (SIMS) has become crucial. Achieving high depth resolution (of the order of 1 nm) is critical in the semiconductor industry today, and various methods have been developed to optimize depth resolution. In this paper, we discuss ultra shallow SIMS depth profiling of B and Ge delta-doped Si samples using low energy (e.g. 500 eV) O/sub 2//sup +/ primary beams. The relationship between depth resolution of the delta layers and surface topography measured by atomic force microscopy (AFM) is studied. The effects of oxygen flooding and sample rotation, used to suppress surface roughening, are also investigated. The various factors that limit the depth resolution in ultra shallow SIMS depth profiling are discussed.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133074570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Intelligent molecular beam epitaxy system for cost-effective manufacturing of compound semiconductor epi-wafers 智能分子束外延系统的成本效益制造化合物半导体外延片
H. Lee
{"title":"Intelligent molecular beam epitaxy system for cost-effective manufacturing of compound semiconductor epi-wafers","authors":"H. Lee","doi":"10.1109/ICSICT.2001.981469","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981469","url":null,"abstract":"In situ non-invasive process monitoring and control during semiconductor epitaxy has been recognized as an enabling technology that can potentially transform existing approaches to epi-wafer manufacturing. We review the evolution of sensor-based MBE systems over the past 10 years, and present recent results of a sensor-based MBE system operating under a production environment. Finally, we discuss some technical challenges towards the realization of a futuristic intelligent epitaxy system.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"25 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133116675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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