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2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)最新文献

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Preparation of low-k nanoporous SiO/sub 2/ films by plasma-enhanced chemical vapor deposition 等离子体增强化学气相沉积制备低钾纳米多孔SiO/ sub2 /薄膜
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.981495
Lenian He, Jin Xu
{"title":"Preparation of low-k nanoporous SiO/sub 2/ films by plasma-enhanced chemical vapor deposition","authors":"Lenian He, Jin Xu","doi":"10.1109/ICSICT.2001.981495","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981495","url":null,"abstract":"Low-dielectric constant (low-k) materials of porous SiO/sub 2/ films were deposited at 300/spl deg/C by plasma enhanced chemical vapor deposition (PE-CVD) using SiH/sub 4/-O/sub 2/ mixtures. The [O/sub 2/]/[SiH/sub 4/] ratio was maintained at 1.5, in which oxide films having a stoichiometric composition can be obtained. It was found that the deposition rate increases linearly with total flow rate of SiH/sub 4/ and O/sub 2/ gases, and the values of k decrease monotonously with increasing deposition rate. No H-related bonds are found in the infrared (IR) spectrum. The value of k for a film prepared at a deposition rate of 56 nm/min was estimated to be 3.4. After an initial annealing at 400/spl deg/C, a thickness loss for the film was near 10%. It suggests that micro-voids exist in the films. These results indicate the possibility to further reduce the k value of PE-CVD porous SiO/sub 2/ films and the potential to incorporate such films in the interconnect structure of ultra larger scale integrated circuits (ULSI).","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121140260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental verification of the principle of operation of ring oscillators of Si complementary vertical dual carrier field effect transistors 硅互补垂直双载流子场效应晶体管环形振荡器工作原理的实验验证
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.981538
Y.Z. Xu, Z.M. Tang, L. Chen, Z.S. Li, Y.B. Li, C.L. Wu, P. Xu, Y.H. Yang, C. Huang, D. Huang
{"title":"Experimental verification of the principle of operation of ring oscillators of Si complementary vertical dual carrier field effect transistors","authors":"Y.Z. Xu, Z.M. Tang, L. Chen, Z.S. Li, Y.B. Li, C.L. Wu, P. Xu, Y.H. Yang, C. Huang, D. Huang","doi":"10.1109/ICSICT.2001.981538","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981538","url":null,"abstract":"Theoretical studies of switching and analog performance of 0.6 volt 20 nm effective channel length Si ASIC of dual carrier field effect transistor and three dimensional field effect transistors will be presented. It will be shown that these field effect transistors can be fabricated by using mature semiconductor technology for linewidth greater than 130 nm.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128119210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Application of hot-carrier reliability simulation to memory and ASIC design 热载波可靠性仿真在存储器和专用集成电路设计中的应用
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982093
P.M. Lee, H. Sato
{"title":"Application of hot-carrier reliability simulation to memory and ASIC design","authors":"P.M. Lee, H. Sato","doi":"10.1109/ICSICT.2001.982093","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982093","url":null,"abstract":"We have applied hot-carrier circuit-level reliability simulation to memory and ASIC logic products. We used two different approaches: for memory products we applied circuit-level simulation to entire circuits to over 12k transistors, so that areas with the worst degradation are not missed due to simulating only certain circuit blocks. We present applications to DRAM and SRAM products, and a design curve to directly relate device-level degradation to circuit degradation. For 0.18 /spl mu/m and 0.14 /spl mu/m logic products, we analyzed simple inverters to create design guidelines for maximum transition time to screen delay library cells to ensure adequate reliability. At 200 MHz, maximum transition time (0-100%) was 0.8 ns (17% or duty) for speed degradation of 5% after a 10-year operating lifetime. Analyzing an 800,000 net product required only a couple of hours. We screened out 30 nets, which were later judged reliable due to their reduced signal duty.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fully-depleted SOI NMOS transistors with p/sup +/-polysilicon gate 具有p/sup +/-多晶硅栅极的全耗尽SOI NMOS晶体管
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.981595
Sun Hai-feng, Liu Xin-yu, Hai Chao-he, Wu De-xin
{"title":"Fully-depleted SOI NMOS transistors with p/sup +/-polysilicon gate","authors":"Sun Hai-feng, Liu Xin-yu, Hai Chao-he, Wu De-xin","doi":"10.1109/ICSICT.2001.981595","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981595","url":null,"abstract":"p/sup +/ polysilicon and n/sup +/ polysilicon were used as the gate material for fully-depleted SOI NMOS transistors. It's found that n-channel transistors with p+ poly gates require lower channel doping levels than their n/sup +/ poly counterparts, leading to easier formation of depleted film and control of the threshold voltage. The low channel doping results in improved source-drain breakdown characteristic.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128612793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Formation and characterization of multi-layered nanocavities in silicon with cascade helium implantation/anneal 级联氦注入/退火下硅中多层纳米空腔的形成与表征
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982155
S. Rangan, S. Ashok, G. Chen, D. Theodore
{"title":"Formation and characterization of multi-layered nanocavities in silicon with cascade helium implantation/anneal","authors":"S. Rangan, S. Ashok, G. Chen, D. Theodore","doi":"10.1109/ICSICT.2001.982155","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982155","url":null,"abstract":"Nanocavities in Si formed by He ion implantation anneal are of interest for impurity gettering in Si technology, localized lifetime control in power devices, and in layer splitting techniques used in water bonding. We have found that sequential thermal anneal is essential to obtain multiple cavity layers with cascade He implants (40-160 keV, 2/spl times/10/sup 15/-4/spl times/10/sup 16/ cm/sup -2/). This behavior is related to the vacancy generation process necessary for cavity formation. Transmission electron microscopy data reveal that, under isothermal anneal, the cavity shape changes from a distinct, aligned hexagonal geometry to a rounded spheroidal shape with increasing anneal time. Photoluminescence (PL) spectra at 77 K reveal a peak at 0.8 eV for all the He-implanted and annealed samples, attributable to band bending around the cavity interfaces. Deep level transient spectroscopy (DLTS) measurements of the cavity region show broad minority carrier (electron in p-type Si) peaks indicative of the presence of defect clusters. Unusual capacitance-temperature (C-T) characteristics with steps and hysterisis are also seen, reflecting metastable behavior arising from change in structural configuration of the cavity defects.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131739131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and simulation of a novel micromachined comb-gimbal gyroscope 一种新型微机械梳架陀螺仪的设计与仿真
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982021
Lufeng Che, Xin Li, B. Xiong, Yaozhi Chen, Yuelin Wang
{"title":"Design and simulation of a novel micromachined comb-gimbal gyroscope","authors":"Lufeng Che, Xin Li, B. Xiong, Yaozhi Chen, Yuelin Wang","doi":"10.1109/ICSICT.2001.982021","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982021","url":null,"abstract":"A novel micromachined comb-gimbal gyroscope is presented, which will be excited by electrostatic forces and the coriolis acceleration induced torsion motion will be read out capacitively. Since electrostatic comb driving and DRIE (deep reactive ion etching) technology are adopted, large driving amplitude can be achieved and sensitivity of gyroscope can be increased. Based on the modal analysis of the gyroscope by FEM method, the structure dimensions are optimized according to resonant frequency matching of the driving mode and detection mode. The fabrication sequences of the gyroscope are discussed in detail.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131880123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pulsed laser annealing of zinc - implanted InP 锌注入InP的脉冲激光退火
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.981471
Chen Chao, M. I. Markevich, F.A. Piskonov, A. Chaplanov, G. Ivlev
{"title":"Pulsed laser annealing of zinc - implanted InP","authors":"Chen Chao, M. I. Markevich, F.A. Piskonov, A. Chaplanov, G. Ivlev","doi":"10.1109/ICSICT.2001.981471","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981471","url":null,"abstract":"The pulsed laser annealing technique can eliminate many induced defects from zinc-implantation InP and change amorphous into mono-crystal on the surface of InP sample. The optimal annealing condition for pulsed ruby laser is that laser power density is about 0-44J/cm/sup 2/ and time width is 70 ns. If the pulsed laser radiating power density is too high or too low, the surface of sample will produce poly-crystal. On the optimal annealing condition, the shallow p-n junction and the high precipitous accepter concentration distribution have been obtained. The maximum accepter concentration will exceed 10/sup 19/cm/sup -3/. The junction depth is less than 0.12 /spl mu/m. The proposed macro-kinetic model can be employed to explain the phenomenon and the physical processes in pulsed laser annealing.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"18 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132026968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Small signal equivalent circuit model of vertical cavity surface emitting lasers 垂直腔面发射激光器的小信号等效电路模型
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982138
Mao Lu-hong, Chen Hong-da, Tang Jun, Liang Kun, Wu Rong-han, N. Hua, Guo Wei-lian, Wu Xia-wan
{"title":"Small signal equivalent circuit model of vertical cavity surface emitting lasers","authors":"Mao Lu-hong, Chen Hong-da, Tang Jun, Liang Kun, Wu Rong-han, N. Hua, Guo Wei-lian, Wu Xia-wan","doi":"10.1109/ICSICT.2001.982138","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982138","url":null,"abstract":"A small signal equivalent circuit model of vertical cavity surface emitting lasers (VCSELs) is given in this paper. The modulation properties of the VCSEL are simulated using this model in the Pspice program. The simulation results are in good agreement with experimental data. An experiment is performed to testify the circuit model.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134142016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test structures based VLSIC yield ramp maximization 基于VLSIC良率斜坡最大化的测试结构
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982070
A. Strojwas, D. Ciplickas, S. Lee
{"title":"Test structures based VLSIC yield ramp maximization","authors":"A. Strojwas, D. Ciplickas, S. Lee","doi":"10.1109/ICSICT.2001.982070","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982070","url":null,"abstract":"This paper addresses a new approach to yield learning of lead products in the most advanced technologies. We start by presenting the classification and evolution of yield loss mechanisms in the most recent and upcoming technology generations. Then we show a spectrum of yield loss characterization methods, from in-line to E-test to product test analysis. The main part of the paper is devoted to the presentation of specially designed test structures for the diagnosis of the dominant yield loss components such as random defects, and systematic and parametric effects.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of Q factor in spiral inductor on silicon 硅基螺旋电感Q因子的优化
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.981467
Zhengyuan Zhang, Z. Wen, Shilu Xu, Zhengfan Zhang, Gang Chen, Shanglian Huang
{"title":"Optimization of Q factor in spiral inductor on silicon","authors":"Zhengyuan Zhang, Z. Wen, Shilu Xu, Zhengfan Zhang, Gang Chen, Shanglian Huang","doi":"10.1109/ICSICT.2001.981467","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981467","url":null,"abstract":"In this paper, analyzing the Q factor of the spiral inductor is done by computer simulation, the results showed that the series resistance R/sub s/ dominates the Q factor of the spiral inductor, and that increasing the substrate silicon resistance is beneficial to increasing the Q factor and decreasing the substrate noise. To increase the Q factor of the spiral inductor, the experiments of decreasing via contact resistance and etching away the substrate silicon under the spiral inductor are done. The compatibility of the 3-dimensional bulk process with the planar IC process has been solved. Using the novel method, the inductor with high Q factor of 8.4 and low series resistance of 3 /spl Omega/ is obtained, and substrate noise is reduced. This method can be used effectively in the design and manufacturing of high performance RF-ICs.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133015264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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