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2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)最新文献

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Full-band Monte Carlo simulation for metal-semiconductor contact with direct tunneling effect 具有直接隧穿效应的金属-半导体接触全带蒙特卡罗模拟
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982045
Lei Sun, G. Du, Xiaoyan Liu, R. Han
{"title":"Full-band Monte Carlo simulation for metal-semiconductor contact with direct tunneling effect","authors":"Lei Sun, G. Du, Xiaoyan Liu, R. Han","doi":"10.1109/ICSICT.2001.982045","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982045","url":null,"abstract":"The metal-semiconductor contact including the quantum mechanical tunneling effect is simulated by the self-consistent ensemble Monte Carlo method. Two-dimension in real space is considered and irregular tetrahedron distribution is used in k-space. A variable G-scheme is used in the self-scattering method. The tunneling currents both under forward and reverse biases are investigated. The results indicate the tunneling effect is of great importance under reverse biases.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117223729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of trapped charges on low-level leakage current in thin silicon dioxide films 二氧化硅薄膜中捕获电荷对低电平泄漏电流的影响
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982058
T.P. Chen, Y. Luo
{"title":"Influence of trapped charges on low-level leakage current in thin silicon dioxide films","authors":"T.P. Chen, Y. Luo","doi":"10.1109/ICSICT.2001.982058","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982058","url":null,"abstract":"In this work, experiments were designed to examine the influence of the trapped charges on SILC in thin SiO/sub 2/ films. It is shown that the release of the trapped electrons in the gate/oxide interface region during the I-V measurement could be responsible for the negative-differential-resistance current at low fields. It is also shown that the positive trapped charges could enhance the DC component of the SILC.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"2 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120837542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Numerical simulation of DC characteristic of InP/InGaAs based optically controlled HEMT 基于InP/InGaAs光控HEMT直流特性的数值模拟
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982153
Fu Renwu, H. Ping, Chen Chao
{"title":"Numerical simulation of DC characteristic of InP/InGaAs based optically controlled HEMT","authors":"Fu Renwu, H. Ping, Chen Chao","doi":"10.1109/ICSICT.2001.982153","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982153","url":null,"abstract":"A new analytical formula of DC characteristics is presented. It shows excellent agreement with experimental data. For the conditions of V/sub /spl psi//=1.4 V and V/sub r/=1.0 V, the channel conductance g/sub d/ is 3.09/spl times/10/sup -2/ mS/mm, the transconductance g/sub m/ is 22.2 mS/mm, and the cut-off frequency f/sub T/ is 16.3 GHz. The mechanism of optically controlled HEMT is explored. Under stable illumination, it shows good agreement with experimental data. The optical responsivity of HEMT is up to 11.4 A/W.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127150282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE model 利用简洁的SOI- spice模型对部分耗尽(PD) SOI CMOS器件中的单晶体管锁存行为进行建模
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982038
J. Kuo, Shih-Chia Lin
{"title":"Modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE model","authors":"J. Kuo, Shih-Chia Lin","doi":"10.1109/ICSICT.2001.982038","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982038","url":null,"abstract":"This paper presents modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE BiCMOS model. As verified by the experimental data and MEDICI simulation results, the concise SOI-SPICE BiCMOS model predicts well the hysteresis and the latched conditions of PD SOI NMOS devices via monitoring V/sub BE/ of the parasitic BJT.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling of front and back gate surface potential of deep-submicro FD-SOI MOSFET 深亚微FD-SOI MOSFET前后栅极表面电位建模
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982032
Cheng Bin Jie, Shao Zhi Biao, Yu Zhong, Shi Ting, Jiang Zheng
{"title":"Modeling of front and back gate surface potential of deep-submicro FD-SOI MOSFET","authors":"Cheng Bin Jie, Shao Zhi Biao, Yu Zhong, Shi Ting, Jiang Zheng","doi":"10.1109/ICSICT.2001.982032","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982032","url":null,"abstract":"This paper extracts the 2D Poisson equation in the subthreshold area by means of a quasi-tripod approximation of longitudinal potential distribution in the silicon film of a FD-SOI device; thus the formulas of both front and back interface of FD-SOI device are obtained. Through the introduction of modified parameters the thesis constructs the surface potential model of the front/back interface of the deep submicron FD device. The model can directly reflect DIBL effect, all of the model formulas are based on physics, and non-infinite series or iterative processes need to be led in, so it has little calculating volume and is very suitable for EDA integrated device models.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127334692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Polarization anisotropy of photoluminescence in corrugated and flat GaAs/AlAs short-period superlattices, grown on faceted [311]A and flat [311]B, [100] GaAs substrates [311]A和[311]B， [100] GaAs衬底上生长的波纹状和扁平GaAs/AlAs短周期超晶格的光致发光偏振各向异性
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982163
G. Lyubas, V. V. Bolotov
{"title":"Polarization anisotropy of photoluminescence in corrugated and flat GaAs/AlAs short-period superlattices, grown on faceted [311]A and flat [311]B, [100] GaAs substrates","authors":"G. Lyubas, V. V. Bolotov","doi":"10.1109/ICSICT.2001.982163","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982163","url":null,"abstract":"The flat and corrugated GaAs/AlAs short-period superlattices (SLs) were studied by polarization resolved-photoluminescence. The phenomenon of photoluminescence polarization anisotropy was observed. The polarization nature is explained by both valence band anisotropy and anisotropy associated with interface corrugation in the case of a [311]A corrugated SLs (CSLs). It was determined that for a GaAs layer thickness from 10.2 to 22 /spl Aring/ the SLs grown on faceted [311]A GaAs substrates contain periodic corrugated GaAs and AlAs layers. The period of corrugation is 32/spl Aring/ along the [011~] direction, the height of corrugation is 10.2 /spl Aring/. This correlates with the model of R. Notzel et al. (1993), and contrasts with the model of M. Wassermeier et al. (1995), where the height of corrugation is 3.4 /spl Aring/. Later the 10.2 /spl Aring/ interface corrugation of GaAs and AlAs layers in these [311]A SLs was directly observed by TEM. The CSLs with average GaAs layer thickness of less than 10.2 /spl Aring/ exhibited considerably lower polarization anisotropy. In this case GaAs quantum dots were formed. The formation of dots reduces the polarization degree. These results are important for development of CSL-based devices sensitive to polarization and operating at high temperatures.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124787721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-k gate dielectrics for scaled CMOS technology 用于缩放CMOS技术的高k栅极电介质
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.981481
T. Ma
{"title":"High-k gate dielectrics for scaled CMOS technology","authors":"T. Ma","doi":"10.1109/ICSICT.2001.981481","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981481","url":null,"abstract":"This paper summarizes our results on several high-k gate dielectrics, including TiO/sub 2/, Ta/sub 2/O/sub 5/, ZrO/sub 2/, HfO/sub 2/, and Al-doped varieties of the above. Among them, TiO/sub 2/ and Ta/sub 2/O/sub 5/ have higher dielectric constants than others, while ZrO/sub 2/ and HfO/sub 2/ are thermodynamically more stable against the formation of SiO/sub 2/ on Si, and the addition of Al raises the temperature for crystallization for all of them. Both MOS capacitors and MOSFET's have been fabricated with these high-k gate dielectrics, and their properties have been studied. We have also utilized the temperature-dependent IN characteristics of these high-k dielectrics to study their current conduction mechanisms and to construct their energy band diagrams.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125783662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The performance improvement of coplanar waveguides by silicon micromachined technology 用硅微加工技术改进共面波导的性能
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982006
Shi Yanling, Lai Zongsheng, Xin Peisheng, Zhu Ziqiang
{"title":"The performance improvement of coplanar waveguides by silicon micromachined technology","authors":"Shi Yanling, Lai Zongsheng, Xin Peisheng, Zhu Ziqiang","doi":"10.1109/ICSICT.2001.982006","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982006","url":null,"abstract":"This article reports the design and fabrication of micromachined microwave transmission lines with suspended structure in terms of the CMOS technology and the post-processing micromachined technology. Samples with 120 /spl Omega/ of characteristic impedance were fabricated through hybrid etching processes. Measurements were performed on the samples using the automatic network analyzer in a wide range of frequency from 1 to 40GHz. The structures with suspended transmission lines showed significant improvement in transmission attenuation.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126166179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influences of various dielectrics materials on p++ silicon diaphragm 不同介电材料对p++硅隔膜的影响
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.982022
Junmiao Wu, Deshu Zou, G. Gao, Lan Li, N. Niu, G. Shen
{"title":"Influences of various dielectrics materials on p++ silicon diaphragm","authors":"Junmiao Wu, Deshu Zou, G. Gao, Lan Li, N. Niu, G. Shen","doi":"10.1109/ICSICT.2001.982022","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.982022","url":null,"abstract":"Effects of various dielectric materials on thermal stress in p++ silicon diaphragm were analyzed. In this work the modeling of thin film deposition based on the finite element analysis (FEA) is described. The theoretical results predict the change of mechanical performance when various dielectric materials were deposited on p++ silicon diaphragm.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"77 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114151900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On "pure self-heating effect" of MOSFET in SOI SOI中MOSFET的“纯自热效应”
2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI: 10.1109/ICSICT.2001.981566
Zheng Taolei, Luo Jinsheng, Zhang Xing
{"title":"On \"pure self-heating effect\" of MOSFET in SOI","authors":"Zheng Taolei, Luo Jinsheng, Zhang Xing","doi":"10.1109/ICSICT.2001.981566","DOIUrl":"https://doi.org/10.1109/ICSICT.2001.981566","url":null,"abstract":"The electrothermal simulation of high-voltage MOSFET in thin SOI for self-heating effects is performed by means of MIDICI, a commercial 2-D numerical simulator. By varying the thermal conductivity of the buried oxide, we can extract the self-heating effects merely from the great rise in thermal resistance of the substrate, which are defined as the pure self-heating effect. The pure self-heating in SOI MOSFET is also presented for universality of the concept.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122021564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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