Modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE model

Abstract

This paper presents modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE BiCMOS model. As verified by the experimental data and MEDICI simulation results, the concise SOI-SPICE BiCMOS model predicts well the hysteresis and the latched conditions of PD SOI NMOS devices via monitoring V/sub BE/ of the parasitic BJT.