利用简洁的SOI- spice模型对部分耗尽(PD) SOI CMOS器件中的单晶体管锁存行为进行建模

2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443) Pub Date : 2001-10-22 DOI:10.1109/ICSICT.2001.982038

J. Kuo, Shih-Chia Lin

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引用次数: 1

摘要

本文采用简洁的SOI- spice BiCMOS模型对部分耗尽(PD) SOI CMOS器件中的单晶体管锁存行为进行建模。实验数据和MEDICI仿真结果验证了简洁的SOI- spice BiCMOS模型通过监测寄生BJT的V/sub BE/能很好地预测PD型SOI NMOS器件的滞回和锁存条件。

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Modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE model

This paper presents modeling of single-transistor latch behavior in partially-depleted (PD) SOI CMOS devices using a concise SOI-SPICE BiCMOS model. As verified by the experimental data and MEDICI simulation results, the concise SOI-SPICE BiCMOS model predicts well the hysteresis and the latched conditions of PD SOI NMOS devices via monitoring V/sub BE/ of the parasitic BJT.

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2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)

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