{"title":"基于VLSIC良率斜坡最大化的测试结构","authors":"A. Strojwas, D. Ciplickas, S. Lee","doi":"10.1109/ICSICT.2001.982070","DOIUrl":null,"url":null,"abstract":"This paper addresses a new approach to yield learning of lead products in the most advanced technologies. We start by presenting the classification and evolution of yield loss mechanisms in the most recent and upcoming technology generations. Then we show a spectrum of yield loss characterization methods, from in-line to E-test to product test analysis. The main part of the paper is devoted to the presentation of specially designed test structures for the diagnosis of the dominant yield loss components such as random defects, and systematic and parametric effects.","PeriodicalId":349087,"journal":{"name":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Test structures based VLSIC yield ramp maximization\",\"authors\":\"A. Strojwas, D. Ciplickas, S. Lee\",\"doi\":\"10.1109/ICSICT.2001.982070\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper addresses a new approach to yield learning of lead products in the most advanced technologies. We start by presenting the classification and evolution of yield loss mechanisms in the most recent and upcoming technology generations. Then we show a spectrum of yield loss characterization methods, from in-line to E-test to product test analysis. The main part of the paper is devoted to the presentation of specially designed test structures for the diagnosis of the dominant yield loss components such as random defects, and systematic and parametric effects.\",\"PeriodicalId\":349087,\"journal\":{\"name\":\"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.2001.982070\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2001.982070","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Test structures based VLSIC yield ramp maximization
This paper addresses a new approach to yield learning of lead products in the most advanced technologies. We start by presenting the classification and evolution of yield loss mechanisms in the most recent and upcoming technology generations. Then we show a spectrum of yield loss characterization methods, from in-line to E-test to product test analysis. The main part of the paper is devoted to the presentation of specially designed test structures for the diagnosis of the dominant yield loss components such as random defects, and systematic and parametric effects.